公开(公告)号：US08230382B2

公开(公告)日：2012-07-24

申请号：US12695494

申请日：2010-01-28

Applicant: Robert J. Gauthier, Jr. ,  Bradford L. Hunter ,  Amol A. Joshi ,  Junjun Li ,  Gregory Joseph Schroer

Inventor： Robert J. Gauthier, Jr. ,  Bradford L. Hunter ,  Amol A. Joshi ,  Junjun Li ,  Gregory Joseph Schroer

IPC: G06F17/50

CPC classification number: G06F17/5036

Abstract: A method, apparatus and program product are provided for simulating a circuit. A plurality of elements of the circuit is represented by device models including pass/fail criteria. A circuit simulation program is executed on a hardware implemented processor where the circuit simulation program is configured to obtain simulation results from the device models in response to applied parameters. The circuit simulation program identifies a failure of one or more of the plurality of elements of the circuit based on the pass/fail criteria of the device models. The circuit simulation program is further configured to output the failures during simulation of the one or more of the plurality of elements that are identified in response to the applied parameters.

Abstract translation: 提供了一种用于模拟电路的方法，装置和程序产品。 电路的多个元件由包括通过/不合格标准的器件模型表示。 在硬件实现的处理器上执行电路仿真程序，其中电路仿真程序被配置为响应于所应用的参数从设备模型获得仿真结果。 电路仿真程序基于设备模型的通过/不合格标准来识别电路的多个元件中的一个或多个元件的故障。 电路仿真程序还被配置为在模拟响应于所应用的参数识别的多个元件中的一个或多个元件期间输出故障。

公开(公告)号：US08217455B2

公开(公告)日：2012-07-10

申请号：US12102032

申请日：2008-04-14

Applicant: Michel J. Abou-Khalil ,  Robert J. Gauthier, Jr. ,  Tom C. Lee ,  Junjun Li ,  Christopher S. Putnam ,  Souvick Mitra

Inventor： Michel J. Abou-Khalil ,  Robert J. Gauthier, Jr. ,  Tom C. Lee ,  Junjun Li ,  Christopher S. Putnam ,  Souvick Mitra

IPC: H01L27/12

CPC classification number: H01L27/1203 ,  H01L27/0248

Abstract: Semiconductor-on-insulator device structures with enhanced electrostatic discharge protection, and design structures for an integrated circuit with device structures exhibiting enhanced electrostatic discharge protection. A device is formed in a body region of a device layer of a semiconductor-on-insulator substrate, which is bounded by an inner peripheral sidewall of an annular dielectric-filled isolation structure that extends from a top surface of the device layer to the insulating layer of the semiconductor-on-insulator substrate. An annular conductive interconnect extends through the body region and the insulating layer to connect the body region with the bulk wafer of the semiconductor-on-insulator substrate. The annular conductive interconnect is disposed inside the inner peripheral sidewall of the isolation structure, which annularly encircles the body region.

Abstract translation: 具有增强的静电放电保护的绝缘体上半导体器件结构以及具有增强的静电放电保护的器件结构的集成电路的设计结构。 一种器件形成在绝缘体上半导体衬底的器件层的体区中，该衬底由环形电介质填充的隔离结构的内周侧壁限定，该隔离结构从器件层的顶表面延伸到绝缘体 绝缘体上半导体衬底的层。 环形导电互连延伸穿过主体区域和绝缘层，以将体区域与绝缘体上半导体衬底的体晶片连接。 环形导电互连件设置在隔离结构的内周侧壁的内侧，环形环绕主体区域。

公开(公告)号：US20120080717A1

公开(公告)日：2012-04-05

申请号：US12898013

申请日：2010-10-05

Applicant: Michel J. ABOU-KHALIL ,  Robert J. GAUTHIER, JR. ,  Tom C. LEE ,  Junjun LI ,  Souvick MITRA ,  Christopher S. PUTNAM

Inventor： Michel J. ABOU-KHALIL ,  Robert J. GAUTHIER, JR. ,  Tom C. LEE ,  Junjun LI ,  Souvick MITRA ,  Christopher S. PUTNAM

IPC: H01L29/747 ,  G06F17/50 ,  H01L21/332

CPC classification number: H01L27/0262 ,  H01L29/747 ,  H01L29/87 ,  H02H9/04

Abstract: Bi-directional back-to-back stacked SCRs for high-voltage pin ESD protection, methods of manufacture and design structures are provided. The device includes a symmetrical bi-directional back-to-back stacked silicon controlled rectifier (SCR). An anode of a first of the back-to-back stacked SCR is connected to an input. An anode of a second of the back-to-back stacked SCR is connected to ground. Cathodes of the first and second of the back-to-back stacked SCR are connected together. Each of the symmetrical bi-directional back-to-back SCRs include a pair of diodes directing current towards the cathodes which, upon application of a voltage, become reverse biased effectively and deactivating elements from one of the symmetrical bi-directional back-to-back SCRs while the diodes of another of the symmetrical bi-directional back-to-back SCRs direct current in the same direction as the reverse biased diodes.

Abstract translation: 提供用于高压针ESD保护的双向背对背堆叠SCR，制造方法和设计结构。 该器件包括对称双向背对背层叠可控硅整流器（SCR）。 背对背堆叠的SCR中的第一个的阳极连接到输入。 背对背堆叠的SCR的第二个的阳极连接到地面。 第一个和第二个背靠背堆叠的SCR的阴极连接在一起。 对称双向背靠背SCR中的每一个包括一对二极管，其引导电流朝向阴极，其在施加电压时有效地变得有效地反向偏置，并且从对称的双向后向SCR中的一个去激活元件， 另一个对称双向背对背SCR的二极管在与反向偏置二极管相同的方向上直流电流，反向SCR。

公开(公告)号：US20120043583A1

公开(公告)日：2012-02-23

申请号：US12859801

申请日：2010-08-20

Applicant: Michel J. ABOU-KHALIL ,  Shunhua T. CHANG ,  Kiran V. CHATTY ,  Robert J. GAUTHIER, JR. ,  Junjun LI ,  Mujahid MUHAMMAD

Inventor： Michel J. ABOU-KHALIL ,  Shunhua T. CHANG ,  Kiran V. CHATTY ,  Robert J. GAUTHIER, JR. ,  Junjun LI ,  Mujahid MUHAMMAD

IPC: H01L27/12 ,  H01L21/84 ,  H01L29/74 ,  H01L21/332 ,  G06F17/50

CPC classification number: H01L29/7412 ,  H01L27/0262

Abstract: A low leakage, low capacitance diode based triggered electrostatic discharge (ESD) silicon controlled rectifiers (SCR), methods of manufacture and design structure are provided. The method includes providing a silicon film on an insulator layer. The method further includes forming isolation regions which extend from an upper side of the silicon layer to the insulator layer. The method further includes forming one or more diodes in the silicon layer, including a p+ region and an n+ region formed in a well bordered by the isolation regions. The isolation regions isolate the one or more diodes in a vertical direction and the insulator layer isolates the one or more diodes from an underlying P or N type substrate, in a horizontal direction.

Abstract translation: 提供了低泄漏，低电容二极管的触发静电放电（ESD）硅控整流器（SCR），制造方法和设计结构。 该方法包括在绝缘体层上提供硅膜。 该方法还包括形成从硅层的上侧延伸到绝缘体层的隔离区域。 该方法还包括在硅层中形成一个或多个二极管，包括形成在由隔离区界定的阱中的p +区和n +区。 隔离区域沿垂直方向隔离一个或多个二极管，并且绝缘体层在水平方向上将一个或多个二极管与下面的P或N型衬底隔离。

公开(公告)号：US08101505B2

公开(公告)日：2012-01-24

申请号：US12135242

申请日：2008-06-09

Applicant: Michel J. Abou-Khalil ,  Robert J. Gauthier, Jr. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam ,  William Tonti

Inventor： Michel J. Abou-Khalil ,  Robert J. Gauthier, Jr. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam ,  William Tonti

IPC: H01L21/479 ,  H01L23/52

CPC classification number: H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention relates to e-fuse devices, and more particularly to a device and method of forming an e-fuse device, the method comprising providing a first conductive layer connected to a second conductive layer, the first and second conductive layers separated by a barrier layer having a first diffusivity different than a second diffusivity of the first conductive layer. A void is created in the first conductive layer by driving an electrical current through the e-fuse device.

Abstract translation: 本发明涉及电熔丝装置，更具体地说，涉及一种形成电熔丝装置的装置和方法，所述方法包括提供连接到第二导电层的第一导电层，所述第一和第二导电层由 阻挡层具有与第一导电层的第二扩散率不同的第一扩散率。 通过驱动电流通过电熔丝装置而在第一导电层中产生空隙。

公开(公告)号：US07956671B2

公开(公告)日：2011-06-07

申请号：US12496002

申请日：2009-07-01

Applicant: Michel J. Abou-Khalil ,  Tom C. Lee ,  Junjun Li ,  Robert J. Gauthier, Jr. ,  Christopher S. Putnam ,  Souvick Mitra

Inventor： Michel J. Abou-Khalil ,  Tom C. Lee ,  Junjun Li ,  Robert J. Gauthier, Jr. ,  Christopher S. Putnam ,  Souvick Mitra

IPC: H01L23/52

CPC classification number: G11C17/16 ,  G11C11/5692 ,  H01L23/5252 ,  H01L23/5256 ,  H01L27/101 ,  H01L27/112 ,  H01L27/11206 ,  H01L45/085 ,  H01L45/1206 ,  H01L45/14 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In one embodiment of an e-fuse programming/re-programming circuit, the e-fuse has two short high atomic diffusion resistance conductor layers positioned on opposite sides and at a same end of a long low atomic diffusion resistance conductor layer. A voltage source is used to vary the polarity and, optionally, the magnitude of voltage applied to the terminals in order to control bi-directional flow of electrons within the long conductor layer and, thereby formation of opens and/or shorts at the long conductor layer-short conductor layer interfaces. The formation of such opens and/or shorts can be used to achieve different programming states. Other circuit structure embodiments incorporate e-fuses with additional conductor layers and additional terminals so as to allow for even more programming states. Also disclosed are embodiments of associated e-fuse programming and re-programming methods.

Abstract translation: 在电熔丝编程/重新编程电路的一个实施例中，电熔丝具有位于长低的原子扩散电阻较长的导体层的相对侧和同一端的两个短的高原子扩散电阻的导体层。 电压源用于改变施加到端子的电压的极性和可选的电压大小，以便控制长导体层内电子的双向流动，从而在长导体上形成开路和/或短路 层 - 短导体层接口。 可以使用这种打开和/或短路的形成来实现不同的编程状态。 其他电路结构实施例包括具有附加导体层和附加端子的电子保险丝，以便允许甚至更多的编程状态。 还公开了相关联的电熔丝编程和重新编程方法的实施例。

公开(公告)号：US07826185B2

公开(公告)日：2010-11-02

申请号：US11692481

申请日：2007-03-28

Applicant: Michel J. Abou-Khalil ,  Robert Gauthier, Jr. ,  Hongmei Li ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam

Inventor： Michel J. Abou-Khalil ,  Robert Gauthier, Jr. ,  Hongmei Li ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam

IPC: H02H9/00 ,  H01C7/12 ,  H02H1/00 ,  H02H1/04 ,  H02H3/22 ,  H02H9/06

CPC classification number: H01L27/0277 ,  H01L27/0262 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An external current injection source is provided to individual fingers of a multi-finger semiconductor device to provide the same trigger voltage across the multiple fingers. For example, the external injection current is supplied to the body of a MOSFET or the gate of a thyristor. The magnitude of the supplied current from each external current injection source is adjusted so that each finger has the same trigger voltage. The external current supply circuit may comprise diodes or an RC triggered MOSFET. The components of the external current supply circuit may be tuned to achieve a desired predetermined trigger voltage across all fingers of the multi-finger semiconductor device.

Abstract translation: 外部电流注入源被提供给多指半导体器件的各个指状物，以跨多个指状物提供相同的触发电压。 例如，外部注入电流被提供给MOSFET的主体或晶闸管的栅极。 调整来自每个外部电流注入源的供给电流的大小，使得每个手指具有相同的触发电压。 外部电流供应电路可以包括二极管或RC触发MOSFET。 可以调谐外部电流供应电路的组件以实现多指半导体器件的所有指状物上期望的预定触发电压。

公开(公告)号：US07746607B2

公开(公告)日：2010-06-29

申请号：US11380525

申请日：2006-04-27

Applicant: Robert J. Gauthier, Jr. ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam

Inventor： Robert J. Gauthier, Jr. ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam

IPC: H02H3/22

CPC classification number: H01L27/0266

Abstract: Electrostatic discharge (ESD) protection device and process for protecting a conventional FET. The device includes at least one FET body forming a resistance, and a triggering circuit coupled to a protection FET and the resistance. The resistance raises a voltage of the at least one body, such that the protection FET is triggered at a voltage lower than the conventional FET.

Abstract translation: 静电放电（ESD）保护装置和保护常规FET的工艺。 该器件包括至少一个形成电阻的FET体，以及耦合到保护FET和电阻的触发电路。 电阻提高至少一个体的电压，使得保护FET在比常规FET低的电压下被触发。

公开(公告)号：US20090256202A1

公开(公告)日：2009-10-15

申请号：US12102032

申请日：2008-04-14

Applicant: Michel J. Abou-Khalil ,  Robert J. Gauthier, JR. ,  Tom C. Lee ,  Junjun Li ,  Christopher S. Putnam ,  Souvick Mitra

Inventor： Michel J. Abou-Khalil ,  Robert J. Gauthier, JR. ,  Tom C. Lee ,  Junjun Li ,  Christopher S. Putnam ,  Souvick Mitra

IPC: H01L29/786

CPC classification number: H01L27/1203 ,  H01L27/0248

Abstract: Semiconductor-on-insulator device structures with enhanced electrostatic discharge protection, and design structures for an integrated circuit with device structures exhibiting enhanced electrostatic discharge protection. A device is formed in a body region of a device layer of a semiconductor-on-insulator substrate, which is bounded by an inner peripheral sidewall of an annular dielectric-filled isolation structure that extends from a top surface of the device layer to the insulating layer of the semiconductor-on-insulator substrate. An annular conductive interconnect extends through the body region and the insulating layer to connect the body region with the bulk wafer of the semiconductor-on-insulator substrate. The annular conductive interconnect is disposed inside the inner peripheral sidewall of the isolation structure, which annularly encircles the body region.

Abstract translation: 具有增强的静电放电保护的绝缘体上半导体器件结构以及具有增强的静电放电保护的器件结构的集成电路的设计结构。 一种器件形成在绝缘体上半导体衬底的器件层的体区中，该衬底由环形电介质填充的隔离结构的内周侧壁限定，该隔离结构从器件层的顶表面延伸到绝缘体 绝缘体上半导体衬底的层。 环形导电互连延伸穿过主体区域和绝缘层，以将体区域与绝缘体上半导体衬底的体晶片连接。 环形导电互连件设置在隔离结构的内周侧壁的内侧，环形环绕主体区域。

公开(公告)号：US20090160013A1

公开(公告)日：2009-06-25

申请号：US11960030

申请日：2007-12-19

Applicant: Michel J. Abou-Khalil ,  Robert J. Gauthier, JR. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam

Inventor： Michel J. Abou-Khalil ,  Robert J. Gauthier, JR. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam

IPC: H01L29/00 ,  H01L21/4763

CPC classification number: H01L23/34 ,  H01L21/743 ,  H01L21/76877 ,  H01L21/84 ,  H01L23/3677 ,  H01L27/0255 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

Abstract: A heat generating component of a semiconductor device is located between two heavily doped semiconductor regions in a semiconductor substrate. The heat generating component may be a middle portion of a diode having a light doping, a lightly doped p-n junction between a cathode and anode of a silicon controlled rectifier, or a resistive portion of a doped semiconductor resistor. At least one thermally conductive via comprising a metal or a non-metallic conductive material is place directly on the heat generating component. Alternatively, a thin dielectric layer may be formed between the heat generating component and the at least one thermally conductive via. The at least one thermally conductive via may, or may not, be connected to a back-end-of-line metal wire, which may be connected to higher level of metal wiring or to a handle substrate through a buried insulator layer.

Abstract translation: 半导体器件的发热元件位于半导体衬底中的两个重掺杂半导体区之间。 发热部件可以是具有轻掺杂的二极管的中间部分，可控硅整流器的阴极和阳极之间的轻掺杂p-n结或掺杂半导体电阻器的电阻部分。 至少一个包含金属或非金属导电材料的导热通孔直接放置在发热部件上。 或者，可以在发热部件和至少一个导热通孔之间形成薄介电层。 至少一个导热通孔可以连接到或可以不连接到后端金属线，其可以通过掩埋绝缘体层连接到较高级别的金属布线或者与手柄基板连接。