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    MODEL BASED SIMULATION AND OPTIMIZATION METHODOLOGY FOR DESIGN CHECKING
    1.
    发明申请
    MODEL BASED SIMULATION AND OPTIMIZATION METHODOLOGY FOR DESIGN CHECKING 有权
    基于模型的模拟和优化方法设计检查

    公开(公告)号：US20110185332A1

    公开(公告)日：2011-07-28

    申请号：US12695494

    申请日：2010-01-28

    申请人： Robert J. Gauthier, JR. ,  Bradford L. Hunter ,  Amol A. Joshi ,  Junjun Li ,  Gregory Joseph Schroer

    发明人： Robert J. Gauthier, JR. ,  Bradford L. Hunter ,  Amol A. Joshi ,  Junjun Li ,  Gregory Joseph Schroer

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5036

    摘要： A method, apparatus and program product are provided for simulating a circuit. A plurality of elements of the circuit is represented by device models including pass/fail criteria. A circuit simulation program is executed on a hardware implemented processor where the circuit simulation program is configured to obtain simulation results from the device models in response to applied parameters. The circuit simulation program identifies a failure of one or more of the plurality of elements of the circuit based on the pass/fail criteria of the device models. The circuit simulation program is further configured to output the failures during simulation of the one or more of the plurality of elements that are identified in response to the applied parameters.

    摘要翻译： 提供了一种用于模拟电路的方法，装置和程序产品。 电路的多个元件由包括通过/不合格标准的器件模型表示。 在硬件实现的处理器上执行电路仿真程序，其中电路仿真程序被配置为响应于所应用的参数从设备模型获得仿真结果。 电路仿真程序基于设备模型的通过/不合格标准来识别电路的多个元件中的一个或多个元件的故障。 电路仿真程序还被配置为在模拟响应于所应用的参数识别的多个元件中的一个或多个元件期间输出故障。

    Model based simulation of electronic discharge and optimization methodology for design checking
    2.
    发明授权
    Model based simulation of electronic discharge and optimization methodology for design checking 有权
    基于模型的电子放电仿真和设计检查优化方法

    公开(公告)号：US08230382B2

    公开(公告)日：2012-07-24

    申请号：US12695494

    申请日：2010-01-28

    申请人： Robert J. Gauthier, Jr. ,  Bradford L. Hunter ,  Amol A. Joshi ,  Junjun Li ,  Gregory Joseph Schroer

    发明人： Robert J. Gauthier, Jr. ,  Bradford L. Hunter ,  Amol A. Joshi ,  Junjun Li ,  Gregory Joseph Schroer

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5036

    摘要： A method, apparatus and program product are provided for simulating a circuit. A plurality of elements of the circuit is represented by device models including pass/fail criteria. A circuit simulation program is executed on a hardware implemented processor where the circuit simulation program is configured to obtain simulation results from the device models in response to applied parameters. The circuit simulation program identifies a failure of one or more of the plurality of elements of the circuit based on the pass/fail criteria of the device models. The circuit simulation program is further configured to output the failures during simulation of the one or more of the plurality of elements that are identified in response to the applied parameters.

    摘要翻译： 提供了一种用于模拟电路的方法，装置和程序产品。 电路的多个元件由包括通过/不合格标准的器件模型表示。 在硬件实现的处理器上执行电路仿真程序，其中电路仿真程序被配置为响应于所应用的参数从设备模型获得仿真结果。 电路仿真程序基于设备模型的通过/不合格标准来识别电路的多个元件中的一个或多个元件的故障。 电路仿真程序还被配置为在模拟响应于所应用的参数识别的多个元件中的一个或多个元件期间输出故障。

    Memory and method for sensing data in a memory using complementary sensing scheme
    3.
    发明授权
    Memory and method for sensing data in a memory using complementary sensing scheme 有权
    用于使用互补感测方案检测存储器中的数据的存储器和方法

    公开(公告)号：US08077533B2

    公开(公告)日：2011-12-13

    申请号：US11337783

    申请日：2006-01-23

    申请人： Bradford L. Hunter ,  Shayan Zhang

    发明人： Bradford L. Hunter ,  Shayan Zhang

    IPC分类号： G11C7/12 ,  G11C7/06 ,  G11C7/08 ,  G11C7/22

    CPC分类号： G11C7/08 ,  G11C7/065 ,  G11C11/413 ,  G11C2207/005

    摘要： In a memory (100), a local data line pair (116, 118) is precharged to a first logic state and a global data line pair (101, 104) is precharged to a second logic state. A selected memory cell is coupled to the local data line pair (116, 118) to develop a differential local data line voltage. The differential local data line voltage is subsequently amplified to form an amplified differential local data line voltage. A selected one of the global data line pair (101, 104) is driven to the first logic state in response to the amplified differential local data line voltage to form a differential global data line voltage.

    摘要翻译： 在存储器（100）中，本地数据线对（116,118）被预充电到第一逻辑状态，并且全局数据线对（101,104）被预充电到第二逻辑状态。 所选择的存储器单元耦合到本地数据线对（116,118）以形成差分本地数据线电压。 差分局部数据线电压随后被放大以形成放大的差分局部数据线电压。 全局数据线对（101,104）中选择的一个被响应于放大的差分本地数据线电压被驱动到第一逻辑状态以形成差分全局数据线电压。

    System and method for controlling signal transitions
    5.
    发明授权
    System and method for controlling signal transitions 有权
    用于控制信号转换的系统和方法

    公开(公告)号：US07598784B2

    公开(公告)日：2009-10-06

    申请号：US11245566

    申请日：2005-10-07

    申请人： Bradford L. Hunter

    发明人： Bradford L. Hunter

    IPC分类号： H03K5/12 ,  H03H11/26

    CPC分类号： H03K5/156 ,  H03K5/05

    摘要： In accordance with the present disclosure, an electronic circuit of an integrated circuit is configured to receive an input signal that has a falling transition and a rising transition and provide a selectable delay of the input signal transitions on its output. The output of the disclosed circuit can provide a falling transition delayed in response to a falling edge control signal control, and a rising transition delayed in response to a rising edge control signal. The disclosed circuit can have a rising transition control circuit (RTCC), a falling transition control circuit (FTCC) and an output circuit.

    摘要翻译： 根据本公开，集成电路的电子电路被配置为接收具有下降转换和上升转换的输入信号，并且在其输出上提供输入信号转换的可选延迟。 所公开的电路的输出可以提供响应于下降沿控制信号控制而延迟的下降转换，以及响应于上升沿控制信号而延迟的上升转变。 所公开的电路可以具有上升跃迁控制电路（RTCC），下降跃迁控制电路（FTCC）和输出电路。

    Wide-Bandwidth Linear Regulator
    6.
    发明申请
    Wide-Bandwidth Linear Regulator 有权
    宽带线性稳压器

    公开(公告)号：US20120313597A1

    公开(公告)日：2012-12-13

    申请号：US13154840

    申请日：2011-06-07

    申请人： Bradford L. Hunter ,  Todd M. Rasmus

    发明人： Bradford L. Hunter ,  Todd M. Rasmus

    IPC分类号： G05F1/575

    CPC分类号： G05F1/575 ,  G05F1/56

    摘要： A linear regulator and a method of regulating a supply voltage are provided. Embodiments include a linear regulator with a first feedback loop and a second feedback loop. The first feedback loop is characterized by a first bandwidth and a first gain. The first feedback loop includes a first amplifier characterized by an output impedance which is significantly reduced in order to maximize the bandwidth of the first feedback loop when driving the capacitance of a control input of a series pass element. The second feedback loop is characterized by a second bandwidth and a second gain. The second feedback loop includes a second amplifier that controls the current in the first amplifier in the first feedback loop.

    摘要翻译： 提供线性调节器和调节电源电压的方法。 实施例包括具有第一反馈回路和第二反馈回路的线性调节器。 第一反馈回路的特征在于第一带宽和第一增益。 第一反馈回路包括第一放大器，其特征在于输出阻抗显着减小，以便在驱动串联通过元件的控制输入的电容时使第一反馈环路的带宽最大化。 第二反馈回路的特征在于第二带宽和第二增益。 第二反馈回路包括控制第一反馈回路中的第一放大器中的电流的第二放大器。

    Controlled reliability in an integrated circuit
    7.
    发明授权
    Controlled reliability in an integrated circuit 有权
    控制集成电路中的可靠性

    公开(公告)号：US07793172B2

    公开(公告)日：2010-09-07

    申请号：US11536342

    申请日：2006-09-28

    申请人： Klas M. Bruce ,  Andrew C. Russell ,  Shayan Zhang ,  Bradford L. Hunter

    发明人： Klas M. Bruce ,  Andrew C. Russell ,  Shayan Zhang ,  Bradford L. Hunter

    IPC分类号： G11C29/00 ,  G11C11/4074

    CPC分类号： G11C29/42 ,  G11C5/147 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028

    摘要： Methods and systems for configuring characteristics associated with at least one portion of a memory array comprising addressable units are provided. In one aspect, a method for controlling a power supply voltage for a memory array comprises detecting whether an error occurred in performing a read operation on an addressable unit of the memory array using a first power supply voltage coupled to the memory array. The method further comprises incrementing an error counter for tracking an error count associated with the memory array and switching the memory array to a second power supply voltage if the error count is equal to or exceeds an error threshold for the memory array. The method further comprises, based on at least one condition, switching the memory array to the first power supply voltage and resetting the error counter to an initial value.

    摘要翻译： 提供了用于配置与包括可寻址单元的存储器阵列的至少一部分相关联的特性的方法和系统。 一方面，一种用于控制存储器阵列的电源电压的方法包括使用耦合到存储器阵列的第一电源电压来检测在对存储器阵列的可寻址单元执行读取操作时是否发生错误。 该方法还包括增加误差计数器以跟踪与存储器阵列相关联的误差计数，并且如果误差计数等于或超过存储器阵列的误差阈值，则将存储器阵列切换到第二电源电压。 该方法还包括基于至少一个条件，将存储器阵列切换到第一电源电压并将错误计数器重置为初始值。

    COMMON MODE FEEDBACK AMPLIFIER WITH SWITCHED DIFFERENTIAL CAPACITOR
    8.
    发明申请
    COMMON MODE FEEDBACK AMPLIFIER WITH SWITCHED DIFFERENTIAL CAPACITOR 失效
    具有开关差分电容器的共模模式反馈放大器

    公开(公告)号：US20090058526A1

    公开(公告)日：2009-03-05

    申请号：US11849625

    申请日：2007-09-04

    申请人： Bradford L. Hunter ,  Gregory J. Schroer

    发明人： Bradford L. Hunter ,  Gregory J. Schroer

    IPC分类号： H03F3/45

    CPC分类号： H03F3/45475 ,  H03F3/45977 ,  H03F2203/45068 ,  H03F2203/45082 ,  H03F2203/45136 ,  H03F2203/45212

    摘要： A structure and related design structure for providing a common mode feedback to a differential amplifier are disclosed. A common mode feedback amplifier is connected to a differential amplifier to provide common mode feedback voltage thereto. An input of the common mode feedback amplifier is shorted to an output terminal of the differential amplifier during a sampling phase, and is coupled to the differential output voltage through two matched capacitors during a holding phase.

    摘要翻译： 公开了一种用于向差分放大器提供共模反馈的结构和相关设计结构。 共模反馈放大器连接到差分放大器以向其提供共模反馈电压。 在采样阶段，共模反馈放大器的输入短路到差分放大器的输出端子，并且在保持阶段通过两个匹配的电容器耦合到差分输出电压。

    Common mode feedback amplifier with switched differential capacitor
    9.
    发明授权
    Common mode feedback amplifier with switched differential capacitor 失效
    具有开关差分电容的共模反馈放大器

    公开(公告)号：US07564307B2

    公开(公告)日：2009-07-21

    申请号：US11849625

    申请日：2007-09-04

    申请人： Bradford L. Hunter ,  Gregory J. Schroer

    发明人： Bradford L. Hunter ,  Gregory J. Schroer

    IPC分类号： H03F3/45

    CPC分类号： H03F3/45475 ,  H03F3/45977 ,  H03F2203/45068 ,  H03F2203/45082 ,  H03F2203/45136 ,  H03F2203/45212

    摘要： A structure and related design structure for providing a common mode feedback to a differential amplifier are disclosed. A common mode feedback amplifier is connected to a differential amplifier to provide common mode feedback voltage thereto. An input of the common mode feedback amplifier is shorted to an output terminal of the differential amplifier during a sampling phase, and is coupled to the differential output voltage through two matched capacitors during a holding phase.

    摘要翻译： 公开了一种用于向差分放大器提供共模反馈的结构和相关设计结构。 共模反馈放大器连接到差分放大器以向其提供共模反馈电压。 在采样阶段，共模反馈放大器的输入短路到差分放大器的输出端子，并且在保持阶段通过两个匹配的电容器耦合到差分输出电压。

    MEMORY SYSTEM WITH REDUNDANT RAM MEMORY CELLS HAVING A DIFFERENT DESIGNED CELL CIRCUIT TOPOLOGY
    10.
    发明申请
    MEMORY SYSTEM WITH REDUNDANT RAM MEMORY CELLS HAVING A DIFFERENT DESIGNED CELL CIRCUIT TOPOLOGY 有权
    具有冗余RAM记忆体的存储系统具有不同的设计细胞电路拓扑学

    公开(公告)号：US20080181034A1

    公开(公告)日：2008-07-31

    申请号：US11627445

    申请日：2007-01-26

    申请人： Bradford L. Hunter ,  James D. Burnett ,  Andrew C. Russell ,  Shayan Zhang

    发明人： Bradford L. Hunter ,  James D. Burnett ,  Andrew C. Russell ,  Shayan Zhang

    IPC分类号： G11C7/00

    CPC分类号： G11C29/846 ,  G11C11/41 ,  G11C11/412 ,  G11C29/816

    摘要： A memory system including a random access memory (RAM) array and a corresponding redundant RAM array which stores information redundant to the RAM array, where a designed cell circuit topology of cells within the redundant RAM array differs from a designed cell circuit topology of cells within the RAM array. The redundant RAM array is selectively accessed when accessing the RAM array to store data to the redundant RAM array for failed cells of the RAM array.

    摘要翻译： 一种存储器系统，包括随机存取存储器（RAM）阵列和相应的冗余RAM阵列，其存储对RAM阵列冗余的信息，其中冗余RAM阵列内的单元的设计单元电路拓扑不同于设计的单元的单元电路拓扑 RAM阵列。 当访问RAM阵列时，有选择地访问冗余RAM阵列，以将数据存储到RAM阵列的故障单元的冗余RAM阵列中。