公开(公告)号：US20210399198A1

公开(公告)日：2021-12-23

申请号：US17467188

申请日：2021-09-04

Applicant: Koucheng Wu

Inventor： Koucheng Wu

IPC: H01L39/22 ,  H01L27/18 ,  H01L39/24

Abstract: A digital circuit includes at least one quantum wire resonant tunneling transistor that includes an emitter terminal, a base terminal, a collector terminal, an emitter region in connection with the emitter terminal, a base region in connection with the base terminal, a collector region in connection with the collector terminal, an emitter barrier region between the emitter region and the base region, and a collector barrier region between the collector region and the base region. At least one of the emitter region, the base region, and the collector region includes a plurality of metal quantum wires.

公开(公告)号：US20110170357A1

公开(公告)日：2011-07-14

申请号：US13072281

申请日：2011-03-25

Applicant: Peter W. Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Han-Rei Ma ,  Koucheng Wu

Inventor： Peter W. Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Han-Rei Ma ,  Koucheng Wu

IPC: G11C16/04

CPC classification number: H01L27/115 ,  G11C11/005 ,  G11C16/0408 ,  G11C16/0416 ,  G11C16/0433 ,  G11C16/10 ,  G11C16/16 ,  G11C16/3436 ,  G11C16/344 ,  G11C16/3445 ,  G11C16/3454 ,  G11C16/3459 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524

Abstract: A novel FLASH-based EEPROM cell, decoder, and layout scheme are disclosed to eliminate the area-consuming divided triple-well in cell array and allows byte-erase and byte-program for high P/E cycles. Furthermore, the process-compatible FLASH cell for EEPROM part can be integrated with FLASH and ROM parts so that a superior combo, monolithic, nonvolatile memory is achieved. Unlike all previous arts, the novel combo nonvolatile memory of the present invention of ROM, EEPROM and FLASH or combination of any two is made of one unified, fully compatible, highly-scalable BN+ cell and unified process. In addition, its cell operation schemes have zero array overhead and zero disturbance during P/E operations. The novel combo nonvolatile memory is designed to meet the need in those markets requiring flexible write size in units of bytes, pages and blocks at a lower cost.

Abstract translation: 公开了一种新颖的基于FLASH的EEPROM单元，解码器和布局方案，以消除单元阵列中的面积消耗的划分三阱，并允许字节擦除和字节程序用于高P / E周期。 此外，用于EEPROM部件的处理兼容FLASH单元可以与FLASH和ROM部件集成，从而实现了优异的组合，单片，非易失性存储器。 与所有以前的技术不同，ROM，EEPROM和FLASH本发明的新颖的组合非易失性存储器或任何两个的组合由一个统一的，完全兼容的，高度可扩展的BN +单元和统一过程组成。 此外，其单元操作方案在P / E操作期间具有零阵列开销和零扰动。 该新颖的组合非易失性存储器旨在满足那些需要灵活的写入大小（以字节，页面和块为单位）以低成本的市场的需求。

公开(公告)号：US20060018164A1

公开(公告)日：2006-01-26

申请号：US11193653

申请日：2005-08-01

Applicant: Koucheng Wu

Inventor： Koucheng Wu

IPC: G11C16/04

CPC classification number: G11C16/3404 ,  G11C11/5628 ,  G11C16/0416 ,  G11C16/0491 ,  H01L21/84 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/1203 ,  H01L29/7881

Abstract: A semiconductor device having an electrically erasable programmable read only memory (EEPROM) comprises a contactless array of EEPROM memory cells disposed in rows and columns and constructed over a silicon-on-insulator wafer. Each EEPROM memory cell comprises a drain region, a source region, a gate region, and a body region. The semiconductor device further comprises a plurality of gate lines each connecting the gate regions of a row of EEPROM memory cells, a plurality of body lines each connecting the body regions of a column of EEPROM memory cells, a plurality of source lines each connecting the source regions of a column of EEPROM memory cells, and a plurality of drain lines each connecting the drain regions of a column of EEPROM memory cells. The source lines and the drain lines are buried lines, and the source regions and the drain regions of a column of EEPROM memory cells are insulated from the source regions and the drain regions of the adjacent columns of EEPROM memory cells.

公开(公告)号：US06963121B2

公开(公告)日：2005-11-08

申请号：US10781383

申请日：2004-02-18

Applicant: Koucheng Wu

Inventor： Koucheng Wu

IPC: H01L21/84 ,  H01L27/095 ,  H01L27/12 ,  H01L29/47 ,  H01L29/812 ,  H01L31/07

CPC classification number: H01L21/84 ,  H01L27/1203

Abstract: A three-terminal semiconductor transistor device comprises a base region formed by a semiconductor material of a first conductivity type at a first concentration, the base region being in contact with a first electrical terminal via a semiconductor material of the second conductivity type at a second concentration, wherein the second concentration is lower than the first concentration. The three-terminal semiconductor transistor device also includes a conductive emitter region in contact with the semiconductor base region, forming a first Schottky barrier junction at the interface of the conductive emitter region and the semiconductor base region. The conductive emitter region is in contact with a second electrical terminal. The three-terminal semiconductor transistor device further includes a conductive collector region in contact with the semiconductor base region, which forms a second Schottky barrier junction at the interface of the conductive collector region and the semiconductor base region. The conductive collector region is in contact with a third electrical terminal. The tunneling current through the first Schottky barrier junction or the second Schottky barrier junction is substantially controlled by the voltage of the semiconductor base region.

Abstract translation: 三端半导体晶体管器件包括由第一浓度的第一导电类型的半导体材料形成的基极区域，所述基极区域经由第二导电类型的半导体材料以第二浓度与第一电端子接触 ，其中所述第二浓度低于所述第一浓度。 三端子半导体晶体管器件还包括与半导体基底区域接触的导电发射极区域，在导电发射极区域和半导体基底区域的界面处形成第一肖特基势垒结。 导电发射极区域与第二电端子接触。 三端子半导体晶体管器件还包括与半导体基极区域接触的导电集电极区域，其在导电集电极区域和半导体基极区域的界面处形成第二肖特基势垒结。 导电集电极区域与第三电端子接触。 穿过第一肖特基势垒结或第二肖特基势垒结的隧道电流基本上由半导体基极区的电压控制。

公开(公告)号：US20050179079A1

公开(公告)日：2005-08-18

申请号：US10781112

申请日：2004-02-18

Applicant: Koucheng Wu

Inventor： Koucheng Wu

IPC: G11C11/56 ,  G11C16/04 ,  G11C16/34 ,  H01L21/8247 ,  H01L21/84 ,  H01L27/115 ,  H01L27/12 ,  H01L29/788

CPC classification number: G11C16/3404 ,  G11C11/5628 ,  G11C16/0416 ,  G11C16/0491 ,  H01L21/84 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/1203 ,  H01L29/7881

Abstract: A semiconductor device having an electrically erasable programmable read only memory (EEPROM) comprises a contactless array of EEPROM memory cells disposed in rows and columns and constructed over a silicon-on-insulator wafer. Each EEPROM memory cell comprises a drain region, a source region, a gate region, and a body region. The semiconductor device further comprises a plurality of gate lines each connecting the gate regions of a row of EEPROM memory cells, a plurality of body lines each connecting the body regions of a column of EEPROM memory cells, a plurality of source lines each connecting the source regions of a column of EEPROM memory cells, and a plurality of drain lines each connecting the drain regions of a column of EEPROM memory cells. The source lines and the drain lines are buried lines, and the source regions and the drain regions of a column of EEPROM memory cells are insulated from the source regions and the drain regions of the adjacent columns of EEPROM memory cells.

Abstract translation: 具有电可擦除可编程只读存储器（EEPROM）的半导体器件包括以行和列布置并构造在绝缘体上硅晶片上的EEPROM存储器单元的非接触阵列。 每个EEPROM存储单元包括漏极区域，源极区域，栅极区域和体区域。 半导体器件还包括多条栅极线，每条栅极线连接一行EEPROM存储器单元的栅极区域，多个体线，每条主体线连接EEPROM存储单元列的主体区域;多个源极线，每条源极线连接源极 一列EEPROM存储单元的区域，以及各自连接EEPROM存储单元列的漏区的多条漏极线。 源极线和漏极线为掩埋线，并且EEPROM存储单元的列的源极区域和漏极区域与EEPROM存储器单元的相邻列的源极区域和漏极区域绝缘。

公开(公告)号：US6087677A

公开(公告)日：2000-07-11

申请号：US966877

申请日：1997-11-10

Applicant: Koucheng Wu

Inventor： Koucheng Wu

IPC: H01L23/525 ,  H01L29/38 ,  H01L23/48

CPC classification number: H01L23/5252 ,  H01L2924/0002

Abstract: The present invention is an antifuse structure comprising an insulation layer between a top conductor and a bottom conductor. The insulation layer has a via. A resistive layer is adjacent the via and a plug is adjacent the resistive layer. The plug is in the via and is also adjacent the top conductor.The present invention also provides a method for fabricating the antifuse on a base. A bottom conductor is deposited on the base. An insulation layer are deposited adjacent the bottom conductor. An antifuse via is etched into the insulation layer. A resistive layer is deposited in the antifuse via. A plug is deposited. The plug extends into the antifuse via. A top conductor is deposited and patterned adjacent the plug.

Abstract translation: 本发明是一种反熔丝结构，其包括在顶部导体和底部导体之间的绝缘层。 绝缘层具有通孔。 电阻层与通孔相邻，并且插塞与电阻层相邻。 插头位于通孔中，并且也与顶部导体相邻。 本发明还提供了一种在基底上制造反熔丝的方法。 底部导体沉积在基座上。 邻近底部导体沉积绝缘层。 反熔丝通孔被蚀刻到绝缘层中。 电阻层沉积在反熔丝通孔中。 一个插头被存放。 插头延伸到反熔丝通孔中。 顶部导体在插头附近沉积并图案化。

公开(公告)号：US11133384B1

公开(公告)日：2021-09-28

申请号：US16852493

申请日：2020-04-19

Applicant: Koucheng Wu

Inventor： Koucheng Wu

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/16 ,  H01L29/423 ,  H01L29/73 ,  H01L29/66 ,  H01L29/04 ,  H01L29/417

Abstract: A semiconductor transistor device includes an emitter region that includes a plurality of metal quantum wires and is connected to an emitter terminal, a base region that includes a plurality of metal quantum wires and is connected to a base terminal, a collector region comprising a plurality of metal quantum wires and is connected to a collector terminal, an emitter barrier region between the emitter region and the base region, and a collector barrier region between the collector region and the base region.

公开(公告)号：US08237212B2

公开(公告)日：2012-08-07

申请号：US13072281

申请日：2011-03-25

Applicant: Peter W. Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Han-Rei Ma ,  Koucheng Wu

Inventor： Peter W. Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Han-Rei Ma ,  Koucheng Wu

IPC: H01L29/788

CPC classification number: H01L27/115 ,  G11C11/005 ,  G11C16/0408 ,  G11C16/0416 ,  G11C16/0433 ,  G11C16/10 ,  G11C16/16 ,  G11C16/3436 ,  G11C16/344 ,  G11C16/3445 ,  G11C16/3454 ,  G11C16/3459 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524

Abstract: A novel FLASH-based EEPROM cell, decoder, and layout scheme are disclosed to eliminate the area-consuming divided triple-well in cell array and allows byte-erase and byte-program for high P/E cycles. Furthermore, the process-compatible FLASH cell for EEPROM part can be integrated with FLASH and ROM parts so that a superior combo, monolithic, nonvolatile memory is achieved. Unlike all previous arts, the novel combo nonvolatile memory of the present invention of ROM, EEPROM and FLASH or combination of any two is made of one unified, fully compatible, highly-scalable BN+cell and unified process. In addition, its cell operation schemes have zero array overhead and zero disturbance during P/E operations. The novel combo nonvolatile memory is designed to meet the need in those markets requiring flexible write size in units of bytes, pages and blocks at a lower cost.

Abstract translation: 公开了一种新颖的基于FLASH的EEPROM单元，解码器和布局方案，以消除单元阵列中的面积消耗的划分三阱，并允许字节擦除和字节程序用于高P / E周期。 此外，用于EEPROM部件的处理兼容FLASH单元可以与FLASH和ROM部件集成，从而实现了优异的组合，单片，非易失性存储器。 与所有以前的技术不同，ROM，EEPROM和FLASH本发明的新颖的组合非易失性存储器或任何两个的组合由一个统一的，完全兼容的，高度可扩展的BN +单元和统一过程组成。 此外，其单元操作方案在P / E操作期间具有零阵列开销和零扰动。 该新颖的组合非易失性存储器旨在满足那些需要灵活的写入大小（以字节，页面和块为单位）以低成本的市场的需求。

公开(公告)号：US07915092B2

公开(公告)日：2011-03-29

申请号：US12001647

申请日：2007-12-12

Applicant: Peter W. Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Han-Rei Ma ,  Koucheng Wu

Inventor： Peter W. Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Han-Rei Ma ,  Koucheng Wu

IPC: H01L21/82

CPC classification number: H01L27/115 ,  G11C11/005 ,  G11C16/0408 ,  G11C16/0416 ,  G11C16/0433 ,  G11C16/10 ,  G11C16/16 ,  G11C16/3436 ,  G11C16/344 ,  G11C16/3445 ,  G11C16/3454 ,  G11C16/3459 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524

Abstract: A novel FLASH-based EEPROM cell, decoder, and layout scheme are disclosed to eliminate the area-consuming divided triple-well in cell array and allows byte-erase and byte-program for high P/E cycles. Furthermore, the process-compatible FLASH cell for EEPROM part can be integrated with FLASH and ROM parts so that a superior combo, monolithic, nonvolatile memory is achieved. Unlike all previous arts, the novel combo nonvolatile memory of the present invention of ROM, EEPROM and FLASH or combination of any two is made of one unified, fully compatible, highly-scalable BN+ cell and unified process. In addition, its cell operation schemes have zero array overhead and zero disturbance during P/E operations. The novel combo nonvolatile memory is designed to meet the need in those markets requiring flexible write size in units of bytes, pages and blocks at a lower cost.

Abstract translation: 公开了一种新颖的基于FLASH的EEPROM单元，解码器和布局方案，以消除单元阵列中的面积消耗的划分三阱，并允许字节擦除和字节程序用于高P / E周期。 此外，用于EEPROM部件的处理兼容FLASH单元可以与FLASH和ROM部件集成，从而实现了优异的组合，单片，非易失性存储器。 与所有以前的技术不同，ROM，EEPROM和FLASH本发明的新颖的组合非易失性存储器或任何两个的组合由一个统一的，完全兼容的，高度可扩展的BN +单元和统一过程组成。 此外，其单元操作方案在P / E操作期间具有零阵列开销和零扰动。 该新颖的组合非易失性存储器旨在满足那些需要灵活的写入大小（以字节，页面和块为单位）以低成本的市场的需求。

公开(公告)号：US20080247230A1

公开(公告)日：2008-10-09

申请号：US11483241

申请日：2006-07-07

Applicant: Peter W. Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Han-Rei Ma ,  Koucheng Wu

Inventor： Peter W. Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Han-Rei Ma ,  Koucheng Wu

IPC: G11C16/06 ,  H01L21/336

CPC classification number: H01L27/115 ,  G11C11/005 ,  G11C16/0408 ,  G11C16/0416 ,  G11C16/0433 ,  G11C16/10 ,  G11C16/16 ,  G11C16/3436 ,  G11C16/344 ,  G11C16/3445 ,  G11C16/3454 ,  G11C16/3459 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524

Abstract: A novel FLASH-based EEPROM cell, decoder, and layout scheme are disclosed to eliminate the area-consuming divided triple-well in cell array and allows byte-erase and byte-program for high P/E cycles. Furthermore, the process-compatible FLASH cell for EEPROM part can be integrated with FLASH and ROM parts so that a superior combo, monolithic, nonvolatile memory is achieved. Unlike all previous arts, the novel combo nonvolatile memory of the present invention of ROM, EEPROM and FLASH or combination of any two is made of one unified, fully compatible, highly-scalable BN+ cell and unified process. In addition, its cell operation schemes have zero array overhead and zero disturbance during P/E operations. The novel combo nonvolatile memory is designed to meet the need in those markets requiring flexible write size in units of bytes, pages and blocks at a lower cost.

Abstract translation: 公开了一种新颖的基于FLASH的EEPROM单元，解码器和布局方案，以消除单元阵列中的面积消耗的划分三阱，并允许字节擦除和字节程序用于高P / E周期。 此外，用于EEPROM部件的处理兼容FLASH单元可以与FLASH和ROM部件集成，从而实现了优异的组合，单片，非易失性存储器。 与所有以前的技术不同，ROM，EEPROM和FLASH本发明的新颖的组合非易失性存储器或任何两个的组合由一个统一的，完全兼容的，高度可扩展的BN +单元和统一过程组成。 此外，其单元操作方案在P / E操作期间具有零阵列开销和零扰动。 该新颖的组合非易失性存储器旨在满足那些需要灵活的写入大小（以字节，页面和块为单位）以低成本的市场的需求。