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86 条记录 (耗时 0.019 秒)

    Method of fabricating n-channel metal-oxide semiconductor transistor
    11.
    发明授权
    Method of fabricating n-channel metal-oxide semiconductor transistor 有权
    制造n沟道金属氧化物半导体晶体管的方法

    公开(公告)号：US08273631B2

    公开(公告)日：2012-09-25

    申请号：US12636788

    申请日：2009-12-14

    申请人： I-Chang Wang ,  Ling-Chun Chou ,  Ming-Tsung Chen

    发明人： I-Chang Wang ,  Ling-Chun Chou ,  Ming-Tsung Chen

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7834 ,  H01L29/665 ,  H01L29/66628

    摘要： A method of fabricating an NMOS transistor, in which, an epitaxial silicon layer is formed before a salicide process is performed, then a nickel layer needed for the salicide process is formed, and, thereafter, a rapid thermal process is performed to allow the nickel layer to react with the epitaxial silicon layer and the silicon substrate under the epitaxial silicon layer to form a nickel silicide layer.

    摘要翻译： 一种制造NMOS晶体管的方法，其中在执行自对准硅化处理之前形成外延硅层，然后形成自对准硅化物处理所需的镍层，然后进行快速热处理，以使镍 层，以在外延硅层下与外延硅层和硅衬底反应以形成硅化镍层。

    Method of fabricating two-step self-aligned contact
    12.
    发明授权
    Method of fabricating two-step self-aligned contact 有权
    制造两步自对准接触的方法

    公开(公告)号：US08129235B2

    公开(公告)日：2012-03-06

    申请号：US11686740

    申请日：2007-03-15

    申请人： Ling-Chun Chou ,  Ming-Tsung Chen ,  Po-Chao Tsao

    发明人： Ling-Chun Chou ,  Ming-Tsung Chen ,  Po-Chao Tsao

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/76897 ,  H01L21/28518 ,  H01L21/76831 ,  H01L21/76895 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of fabricating a self-aligned contact is provided. A first dielectric layer is formed on a substrate having a contact region therein. Next, a lower hole corresponding to the contact region is formed in the first dielectric layer. Thereafter, a second dielectric layer is formed on the first dielectric layer, and then an upper hole self-aligned to and communicated with the lower hole is formed in the second dielectric layer, wherein the upper hole and the lower hole constitute a self-aligned contact hole. Afterwards, the self-aligned contact hole is filled with a conductive layer.

    摘要翻译： 提供一种制造自对准接触的方法。 在其中具有接触区域的基板上形成第一电介质层。 接下来，在第一电介质层中形成与接触区域对应的下孔。 此后，在第一电介质层上形成第二电介质层，然后在第二电介质层中形成自对准并与下孔连通的上孔，其中上孔和下孔构成自对准 接触孔。 然后，自对准接触孔填充有导电层。

    FLATTENING MECHANISM FOR DRY FILM LAMINATOR
    13.
    发明申请
    FLATTENING MECHANISM FOR DRY FILM LAMINATOR 有权
    干膜机层压机构

    公开(公告)号：US20110186239A1

    公开(公告)日：2011-08-04

    申请号：US12699070

    申请日：2010-02-03

    申请人： Chin-Sen LAI ,  Ming-Tsung Chen

    发明人： Chin-Sen LAI ,  Ming-Tsung Chen

    IPC分类号： B32B43/00

    CPC分类号： B32B43/00 ,  Y10T156/16

    摘要： A flattening mechanism for dry film laminator includes a lower member connected to a dry film laminator. The lower member has a base portion formed thereon. The base portion has a plurality of air holes defined therein. The lower member has a lifting holder movably disposed thereon for holding a wafer. The wafer has a dry film disposed thereon. An upper member is movably disposed above the lower member. The upper member has a pressing portion disposed on a bottom thereof. The pressing portion has a steel plate disposed thereon and a first electric heating layer mounted on a top of the steel. A release film is movably guided between the upper member and the lower member, such that the wafer is lifted to press against the steel plate via the release film for enhancing a lamination of the dry film to the wafer and flattening the dry film.

    摘要翻译： 用于干膜层压机的压扁机构包括连接到干膜层压机的下部构件。 下部构件具有形成在其上的基部。 基部具有限定在其中的多个气孔。 下部构件具有可移动地设置在其上用于保持晶片的提升保持器。 晶片具有设置在其上的干膜。 上部构件可移动地设置在下部构件的上方。 上部构件具有设置在其底部的按压部。 按压部具有设置在其上的钢板和安装在钢的顶部上的第一电加热层。 剥离膜在上部构件和下部构件之间被可移动地引导，使得晶片被提升以经由隔离膜压靠钢板，用于增强干膜对晶片的层压并使干膜变平。

    STATIC MEASURING METHOD OF ELECTRICAL REFERENCES OF THREE-PHASE PERMANENT MAGNET SYNCHRONOUS MOTOR
    16.
    发明申请
    STATIC MEASURING METHOD OF ELECTRICAL REFERENCES OF THREE-PHASE PERMANENT MAGNET SYNCHRONOUS MOTOR 有权
    三相永磁同步电机电气参考静态测量方法

    公开(公告)号：US20090157336A1

    公开(公告)日：2009-06-18

    申请号：US11957722

    申请日：2007-12-17

    申请人： Ming-Tsung CHEN

    发明人： Ming-Tsung CHEN

    IPC分类号： G01R31/34

    CPC分类号： G01R31/34

    摘要： A method for measuring a resistance and an inductance of a permanent magnet synchronous motor (PMSM) in a static state includes inputting a rated current of the PMSM and 150% of the rated current at a state of locking an axle of the PMSM, recording corresponding voltages V100% and V150%, and dividing the voltage difference with the current difference to obtain the resistance of the PMSM. The method continues dividing an electrical period into six voltage vectors at a state of vector controlling, and performing four voltage cycles under every the voltage vector. The voltage cycle includes step outputting a quarter of the voltage V150%, and outputting the voltage V150% after the current being stable. After one of the six voltage vectors being finished, the method switches the other voltage vector and repeats the voltage cycles, and the method is completed till all of the six voltage vectors being finished. Finally, the method continues to compare rising times of the voltage vectors and convert the rising times to inductances, and to define the maximum of the inductances as an inductance of a q axis and to define the minimum of the inductances as an inductance of a d axis.

    摘要翻译： 用于测量静止状态的永磁同步电动机（PMSM）的电阻和电感的方法包括在PMSM的轴的锁定状态下输入PMSM的额定电流和额定电流的150％，记录相应的 电压V100％和V150％，并且将电压差除以电流差以获得PMSM的电阻。 该方法在矢量控制的状态下将电周期分为六个电压矢量，并且在每个电压矢量下执行四个电压周期。 电压周期包括步进输出电压V150％的四分之一，并且在电流稳定后输出电压V150％。 在六个电压矢量中的一个完成之后，该方法切换另一个电压矢量并重复电压周期，并且完成所有六个电压矢量的所有方法。 最后，该方法继续比较电压矢量的上升时间并将上升时间转换为电感，并将电感的最大值定义为q轴的电感，并将电感的最小值定义为d轴的电感。

    METHOD OF FABRICATING NICKEL SILICIDE
    18.
    发明申请
    METHOD OF FABRICATING NICKEL SILICIDE 有权
    制备尼龙硅胶的方法

    公开(公告)号：US20070167009A1

    公开(公告)日：2007-07-19

    申请号：US11685209

    申请日：2007-03-13

    申请人： Yi-Wei Chen ,  Chao-Ching Hsieh ,  Yi-Yiing Chiang ,  Tzung-Yu Hung ,  Yu-Lan Chang ,  Po-Chao Tsao ,  Chang-Chi Huang ,  Ming-Tsung Chen

    发明人： Yi-Wei Chen ,  Chao-Ching Hsieh ,  Yi-Yiing Chiang ,  Tzung-Yu Hung ,  Yu-Lan Chang ,  Po-Chao Tsao ,  Chang-Chi Huang ,  Ming-Tsung Chen

    IPC分类号： H01L21/44

    CPC分类号： H01L29/665 ,  H01L21/324 ,  H01L29/4933

    摘要： A semiconductor device having nickel suicide and a method for fabricating nickel silicide. A semiconductor substrate having a plurality of doped regions is provided. Subsequently, a nickel layer is formed on the semiconductor substrate, and a first rapid thermal process (RTP) is performed to react the nickel layer with the doped regions disposed there under. Thereafter, the unreacted nickel layer is removed, and a second rapid thermal process is performed to form a semiconductor device having nickel silicide. The second rapid thermal process is a spike anneal process whose process temperature is between 400 and 600° C.

    摘要翻译： 一种具有镍硅化物的半导体器件和一种制造硅化镍的方法。 提供具有多个掺杂区域的半导体衬底。 随后，在半导体衬底上形成镍层，并进行第一快速热处理（RTP）以使镍层与设置在其下方的掺杂区域反应。 此后，除去未反应的镍层，进行第二快速热处理以形成具有硅化镍的半导体器件。 第二快速热处理是工艺温度在400和600℃之间的尖峰退火工艺。

    Metal oxide semiconductor transistor
    19.
    发明授权
    Metal oxide semiconductor transistor 有权
    金属氧化物半导体晶体管

    公开(公告)号：US07214988B2

    公开(公告)日：2007-05-08

    申请号：US11162693

    申请日：2005-09-20

    申请人： Po-Chao Tsao ,  Chang-Chi Huang ,  Ming-Tsung Chen ,  Yi-Yiing Chiang ,  Yu-Lan Chang ,  Chung-Ju Lee ,  Chih-Ning Wu ,  Kuan-Yang Liao

    发明人： Po-Chao Tsao ,  Chang-Chi Huang ,  Ming-Tsung Chen ,  Yi-Yiing Chiang ,  Yu-Lan Chang ,  Chung-Ju Lee ,  Chih-Ning Wu ,  Kuan-Yang Liao

    IPC分类号： H01L29/76

    CPC分类号： H01L29/6653 ,  H01L21/28518 ,  H01L21/31111 ,  H01L29/6659

    摘要： A method for forming a metal oxide semiconductor (MOS) transistor is provided. First, a gate structure is formed over a substrate. Then, offset spacers are formed on respective sidewalls of the gate structure. A first ion implantation process is performed to form a lightly doped drain (LDD) in the substrate beside the gate structure. Other spacers are formed on respective sidewalls of the offset spacers. Thereafter, a second ion implantation process is performed to form source/drain region in the substrate beside the spacers. Then, a metal silicide layer is formed on the surface of the source and the drain. An oxide layer is formed on the surface of the metal silicide layer. The spacers are removed and an etching stop layer is formed on the substrate. With the oxide layer over the metal silicide layer, the solvent for removing the spacers is prevented from damaging the metal silicide layer.

    摘要翻译： 提供一种用于形成金属氧化物半导体（MOS）晶体管的方法。 首先，在基板上形成栅极结构。 然后，在栅极结构的相应侧壁上形成偏移间隔物。 执行第一离子注入工艺以在栅极结构旁边的衬底中形成轻掺杂漏极（LDD）。 在偏置间隔物的相应侧壁上形成其它间隔物。 此后，进行第二离子注入工艺以在衬垫旁边的衬垫上形成源极/漏极区域。 然后，在源极和漏极的表面上形成金属硅化物层。 在金属硅化物层的表面上形成氧化物层。 去除间隔物，并在衬底上形成蚀刻停止层。 通过金属硅化物层上的氧化物层，可以防止用于除去间隔物的溶剂损坏金属硅化物层。

    SILICIDE PROCESS UTILIZING PRE-AMORPHIZATION IMPLANT AND SECOND SPACER
    20.
    发明申请
    SILICIDE PROCESS UTILIZING PRE-AMORPHIZATION IMPLANT AND SECOND SPACER 有权
    使用预扩展植入物和第二间隔物的硅化工艺

    公开(公告)号：US20060252213A1

    公开(公告)日：2006-11-09

    申请号：US11456091

    申请日：2006-07-07

    申请人： Ming-Tsung Chen

    发明人： Ming-Tsung Chen

    IPC分类号： H01L21/336

    CPC分类号： H01L21/26506 ,  H01L21/26586 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

    摘要： A gate electrode is formed on a substrate with a gate insulating layer therebetween. A liner is then deposited on sidewalls of the gate electrode. Source/drain extensions are implanted into the substrate. A first spacer is then formed on the liner. Deep source/drain are implanted into the substrate. A second spacer is formed at the foot of the first spacer. A tilt-angle pre-amorphization implant (PAI) is conducted to form an amorphized layer next to the second spacer. A metal layer is then sputtered on the amorphized layer. The metal layer reacts with the amorphized layer to form a metal silicide layer thereto.

    摘要翻译： 栅电极形成在基板上，栅极绝缘层在其间。 然后将衬垫沉积在栅电极的侧壁上。 源极/漏极延伸部分植入到衬底中。 然后在衬套上形成第一间隔件。 将深源极/漏极注入到衬底中。 第二间隔件形成在第一间隔件的底部。 进行倾斜角度前非晶化植入（PAI）以在第二间隔物旁边形成非晶化层。 然后将金属层溅射在非晶化层上。 金属层与非晶化层反应以形成金属硅化物层。