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11.发明授权公开(公告)号：US08176235B2
公开(公告)日：2012-05-08
申请号：US12631505
申请日：2009-12-04
IPC分类号： G06F12/00
CPC分类号： G06F12/0246
摘要： Enhanced write performance for non-volatile memories including a memory system that includes a receiver for receiving a data rate of a data sequence to be written to a non-volatile flash memory device. The memory system also includes a physical page selector for selecting a physical address of an invalid previously written memory page from a group of physical addresses of invalid previously written memory pages located on the non-volatile memory device, and for determining if the number of free bits in the invalid previously written memory page at the selected physical address is greater than or equal to the data rate. The memory system also includes a transmitter for outputting the selected physical address of the invalid previously written memory page, the outputting in response to the physical page selector determining that the number of free bits is greater than or equal to the data rate.
摘要翻译： 对于非易失性存储器的增强的写入性能，包括存储器系统，该存储器系统包括用于接收要写入非易失性闪速存储器件的数据序列的数据速率的接收器。 存储器系统还包括物理页面选择器，用于从位于非易失性存储器设备上的无效的先前写入的存储器页面的一组物理地址中选择无效的先前写入的存储器页面的物理地址，并且用于确定是否有空闲数量 在所选物理地址处的无效的先前写入的存储器页中的位大于或等于数据速率。 存储器系统还包括用于输出无效的先前写入的存储器页面的所选物理地址的发射器，响应于物理页选择器确定空闲位的数量大于或等于数据速率的输出。
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公开(公告)号：US20110228600A1
公开(公告)日：2011-09-22
申请号：US13150690
申请日：2011-06-01
申请人： Matthew J. Breitwisch , Roger W. Cheek , Stefanie R. Chiras , Ibrahim M. Elfadel , Michele M. Franceschini , John P. Karidis , Luis A. Lastras-Montano , Thomas Mittelholzer , Mayank Sharma
发明人： Matthew J. Breitwisch , Roger W. Cheek , Stefanie R. Chiras , Ibrahim M. Elfadel , Michele M. Franceschini , John P. Karidis , Luis A. Lastras-Montano , Thomas Mittelholzer , Mayank Sharma
IPC分类号： G11C11/21
CPC分类号： G11C29/02 , G11C13/0004 , G11C13/0064 , G11C13/0069 , G11C29/021 , G11C29/028 , G11C2013/0092
摘要： Systems, methods, and devices for iteratively writing contents to memory locations are provided. A statistical model is used to determine a sequence of pulses to write desired contents to a memory location. The contents can be expressed as a resistance value in a range to store one or more bits in a memory cell. For phase change memory, an adaptive reset pulse and one or more annealing pulses are selected based on a desired resistance range. Reading the resistance value of the memory cell can provide feedback to determine adjustments in an overall pulse application strategy. The statistical model and a look up table can be used to select and modify pulses. Adaptively updating the statistical model and look up table may reduce the number of looping iterations to shift the resistance value of the memory cell into the desired resistance range.
摘要翻译： 提供了用于向内存位置迭代地写入内容的系统，方法和设备。 统计模型用于确定将所需内容写入存储器位置的脉冲序列。 内容可以表示为在存储单元中存储一个或多个位的范围内的电阻值。 对于相变存储器，基于期望的电阻范围来选择自适应复位脉冲和一个或多个退火脉冲。 读取存储器单元的电阻值可提供反馈以确定整体脉冲应用策略中的调整。 统计模型和查询表可用于选择和修改脉冲。 自适应地更新统计模型和查找表可以减少循环迭代的次数以将存储器单元的电阻值移动到期望的电阻范围。
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13.发明申请公开(公告)号：US20110138105A1
公开(公告)日：2011-06-09
申请号：US12631505
申请日：2009-12-04
CPC分类号： G06F12/0246
摘要： Enhanced write performance for non-volatile memories including a memory system that includes a receiver for receiving a data rate of a data sequence to be written to a non-volatile flash memory device. The memory system also includes a physical page selector for selecting a physical address of an invalid previously written memory page from a group of physical addresses of invalid previously written memory pages located on the non-volatile memory device, and for determining if the number of free bits in the invalid previously written memory page at the selected physical address is greater than or equal to the data rate. The memory system also includes a transmitter for outputting the selected physical address of the invalid previously written memory page, the outputting in response to the physical page selector determining that the number of free bits is greater than or equal to the data rate.
摘要翻译： 对于非易失性存储器的增强的写入性能，包括存储器系统，该存储器系统包括用于接收要写入非易失性闪速存储器件的数据序列的数据速率的接收器。 存储器系统还包括物理页面选择器，用于从位于非易失性存储器设备上的无效的先前写入的存储器页面的一组物理地址中选择无效的先前写入的存储器页面的物理地址，并且用于确定是否有空闲数量 在所选物理地址处的无效的先前写入的存储器页中的位大于或等于数据速率。 存储器系统还包括用于输出无效的先前写入的存储器页面的所选物理地址的发射器，响应于物理页选择器确定空闲位的数量大于或等于数据速率的输出。
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14.发明授权Coding techniques for improving the sense margin in content addressable memories 有权用于改善内容可寻址存储器中的检测边缘的编码技术公开(公告)号：US07881089B2
公开(公告)日：2011-02-01
申请号：US12392049
申请日：2009-02-24
IPC分类号： G11C15/00
CPC分类号： G11C15/00 , G11C7/1006 , G11C13/0004 , G11C15/02 , G11C15/046
摘要： A content addressable memory using encoded data words and search words, and techniques for operating such device. In one embodiment, the data word is transformed into a code word guaranteeing a mismatch of at least two code word bits of different binary values during the memory search operation when the data word does not match a search word. In another embodiment, the search word is transformed into a search code such that the Hamming distance between the code word and the search code is greater than a given threshold when there is a mismatch of at least one bit between the data word and the search word.
摘要翻译： 使用编码数据字和搜索词的内容可寻址存储器，以及用于操作这样的设备的技术。 在一个实施例中，当数据字与搜索词不匹配时，数据字被转换成保证在存储器搜索操作期间不同二进制值的至少两个码字位的失配的码字。 在另一个实施例中，搜索词被变换成搜索码，使得当数据字和搜索词之间存在至少一个比特的不匹配时，码字和搜索码之间的汉明距离大于给定阈值 。
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公开(公告)号：US20100214829A1
公开(公告)日：2010-08-26
申请号：US12391693
申请日：2009-02-24
申请人： Matthew J. Breitwisch , Roger W. Cheek , Stefanie R. Chiras , Ibrahim M. Elfadel , Michele M. Franceschini , John P. Karidis , Luis A. Lastras-Montano , Thomas Mittelholzer , Mayank Sharma
发明人： Matthew J. Breitwisch , Roger W. Cheek , Stefanie R. Chiras , Ibrahim M. Elfadel , Michele M. Franceschini , John P. Karidis , Luis A. Lastras-Montano , Thomas Mittelholzer , Mayank Sharma
IPC分类号： G11C11/00
CPC分类号： G11C29/02 , G11C13/0004 , G11C13/0064 , G11C13/0069 , G11C29/021 , G11C29/028 , G11C2013/0092
摘要： Systems, methods, and devices for iteratively writing contents to memory locations are provided. A statistical model is used to determine a sequence of pulses to write desired contents to a memory location. The contents can be expressed as a resistance value in a range to store one or more bits in a memory cell. For phase change memory, an adaptive reset pulse and one or more annealing pulses are selected based on a desired resistance range. Reading the resistance value of the memory cell can provide feedback to determine adjustments in an overall pulse application strategy. The statistical model and a look up table can be used to select and modify pulses. Adaptively updating the statistical model and look up table may reduce the number of looping iterations to shift the resistance value of the memory cell into the desired resistance range.
摘要翻译： 提供了用于向内存位置迭代地写入内容的系统，方法和设备。 统计模型用于确定将所需内容写入存储器位置的脉冲序列。 内容可以表示为在存储单元中存储一个或多个位的范围内的电阻值。 对于相变存储器，基于期望的电阻范围来选择自适应复位脉冲和一个或多个退火脉冲。 读取存储器单元的电阻值可提供反馈以确定整体脉冲应用策略中的调整。 统计模型和查询表可用于选择和修改脉冲。 自适应地更新统计模型和查找表可以减少循环迭代的次数以将存储器单元的电阻值移动到期望的电阻范围。
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16.发明申请CODING TECHNIQUES FOR IMPROVING THE SENSE MARGIN IN CONTENT ADDRESSABLE MEMORIES 有权用于改善内容可寻址存储器中的感应信号的编码技术公开(公告)号：US20100214811A1
公开(公告)日：2010-08-26
申请号：US12392049
申请日：2009-02-24
IPC分类号： G11C15/00
CPC分类号： G11C15/00 , G11C7/1006 , G11C13/0004 , G11C15/02 , G11C15/046
摘要： A content addressable memory using encoded data words and search words, and techniques for operating such device. In one embodiment, the data word is transformed into a code word guaranteeing a mismatch of at least two code word bits of different binary values during the memory search operation when the data word does not match a search word. In another embodiment, the search word is transformed into a search code such that the Hamming distance between the code word and the search code is greater than a given threshold when there is a mismatch of at least one bit between the data word and the search word.
摘要翻译： 使用编码数据字和搜索词的内容可寻址存储器，以及用于操作这样的设备的技术。 在一个实施例中，当数据字与搜索词不匹配时，数据字被转换成保证在存储器搜索操作期间不同二进制值的至少两个码字位的失配的码字。 在另一个实施例中，搜索词被变换成搜索码，使得当数据字和搜索词之间存在至少一个比特的不匹配时，码字和搜索码之间的汉明距离大于给定阈值 。
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公开(公告)号：US09071277B1
公开(公告)日：2015-06-30
申请号：US13556561
申请日：2012-07-24
CPC分类号： H03M13/15 , H03M13/152 , H03M13/17 , H03M13/2906 , H04L1/0045
摘要： Correction of structured burst errors in data is provided by a system that includes an encoder and is configured for performing a method. The method includes receiving data that includes a plurality of subsets of data. The data is encoded by an encoder using a combination of a first error correcting code and a second error correcting code. The first error correcting code is configured to provide error recovery from a structured burst error in one of the subsets of data, the structured burst error having a length less than a specified maximum length. The second error correcting code is configured to extend the first error correcting code to provide error recovery from the structured burst error in any of the subsets of data. The encoded data is output.
摘要翻译： 数据中的结构化突发错误的校正由包括编码器并且被配置为执行方法的系统提供。 该方法包括接收包括多个数据子集的数据。 数据由编码器使用第一纠错码和第二纠错码的组合进行编码。 第一纠错码被配置为从数据子集之一中的结构化突发错误提供错误恢复，结构化突发错误的长度小于指定的最大长度。 第二纠错码被配置为扩展第一纠错码，以便在数据子集中的结构化突发错误中提供错误恢复。 输出编码数据。
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公开(公告)号：US08868978B2
公开(公告)日：2014-10-21
申请号：US13396020
申请日：2012-02-14
IPC分类号： G06F11/00
CPC分类号： G11C29/56008 , G06F11/2289 , G06F11/3409 , G11C16/349
摘要： Discarded memory devices unfit for an original purpose can be reclaimed for reuse for another purpose. The discarded memory devices are tested and evaluated to determine the level of performance degradation therein. A set of an alternate usage and an information encoding scheme to facilitate a reuse of the tested memory device is identified based on the evaluation of the discarded memory device. A memory chip controller may be configured to facilitate usage of reclaimed memory devices by enabling a plurality of encoding schemes therein. Further, a memory device can be configured to facilitate diagnosis of the functionality, and to facilitate usage as a discarded memory unit. Waste due to discarded memory devices can be thereby reduced.
摘要翻译： 废弃的不适合原始目的的存储设备可以回收再利用用于另一目的。 对废弃的存储器件进行测试和评估，以确定其中性能下降的程度。 基于对废弃的存储器件的评估来识别一组替代使用和信息编码方案，以便于重新使用被测试的存储器件。 存储器芯片控制器可以被配置为通过使能其中的多个编码方案来促进再生存储器件的使用。 此外，存储器装置可以被配置为便于诊断功能，并且便于作为丢弃的存储器单元的使用。 因此可以减少由于废弃的存储器件造成的浪费。
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公开(公告)号：US08848471B2
公开(公告)日：2014-09-30
申请号：US13569486
申请日：2012-08-08
申请人： Michele M. Franceschini , Hillery C. Hunter , Ashish Jagmohan , Charles A. Kilmer , Kyu-hyoun Kim , Luis A. Lastras , Moinuddin K. Qureshi
发明人： Michele M. Franceschini , Hillery C. Hunter , Ashish Jagmohan , Charles A. Kilmer , Kyu-hyoun Kim , Luis A. Lastras , Moinuddin K. Qureshi
CPC分类号： G11C29/50 , G11C11/406 , G11C29/023 , G11C29/028 , G11C29/50016
摘要： A method for determining an optimized refresh rate involves testing a refresh rate on rows of cells, determining an error rate of the rows, evaluating the error rate of the rows; and repeating these steps for a decreased refresh rate until the error rate is greater than a constraint, at which point a slow refresh rate is set.
摘要翻译： 用于确定优化的刷新速率的方法涉及测试单元行的刷新率，确定行的错误率，评估行的错误率; 并重复这些步骤以减少刷新率，直到错误率大于约束，此时设置较慢的刷新率。
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公开(公告)号：US08685785B2
公开(公告)日：2014-04-01
申请号：US13619493
申请日：2012-09-14
IPC分类号： H01L21/02
CPC分类号： G11C8/10 , G11C11/5678 , G11C13/0004 , G11C13/0069 , G11C2013/0083 , H01L27/2463 , H01L45/06 , H01L45/1226 , H01L45/144 , H01L45/1675
摘要： A method of manufacturing a phase change memory cell on a substrate. The method includes: etching a first trench in the substrate; depositing a first conductor layer in the first trench; depositing a first insulator layer over the first conductor layer in the first trench; etching a second trench in the substrate at an angle to the first trench; depositing a second insulator layer in the second trench; depositing a second conductor layer over the second insulator layer in the second trench; and depositing phase change material. The deposited phase change material is in contact with the first conductor layer and the second conductor layer.
摘要翻译： 一种在衬底上制造相变存储单元的方法。 该方法包括：蚀刻衬底中的第一沟槽; 在第一沟槽中沉积第一导体层; 在所述第一沟槽中的所述第一导体层上沉积第一绝缘体层; 以与第一沟槽成一定角度蚀刻衬底中的第二沟槽; 在所述第二沟槽中沉积第二绝缘体层; 在所述第二沟槽中的所述第二绝缘体层上沉积第二导体层; 并沉积相变材料。 沉积的相变材料与第一导体层和第二导体层接触。
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