公开(公告)号：US06822301B2

公开(公告)日：2004-11-23

申请号：US10210132

申请日：2002-07-31

Applicant: Michael Maldei ,  Jinhwan Lee ,  Guenter Gerstmeier ,  Brian Cousineau ,  Jon S. Berry, II ,  Steven M. Baker ,  Malati Hedge

Inventor： Michael Maldei ,  Jinhwan Lee ,  Guenter Gerstmeier ,  Brian Cousineau ,  Jon S. Berry, II ,  Steven M. Baker ,  Malati Hedge

IPC: H01L2976

CPC classification number: H01L27/1052 ,  H01L21/3185 ,  H01L27/105 ,  H01L27/10876 ,  H01L27/10891 ,  H01L27/10894

Abstract: A process for fabricating a semiconductor structure, wherein the semiconductor structure includes a core region and a periphery region. The core region includes a plurality of transistors and the periphery region includes a plurality of transistors. The process includes depositing a middle-of-line liner using plasma enhanced chemical vapor deposition overlying the semiconductor structure. By using a plasma enhanced chemical vapor deposition the amount of MOL liner deposited in the core region and the periphery region can be controlled depending on the distances between transistors in the core region and periphery region.

Abstract translation: 一种制造半导体结构的方法，其中半导体结构包括芯区域和周边区域。 芯区域包括多个晶体管，并且周边区域包括多个晶体管。 该方法包括使用覆盖半导体结构的等离子体增强化学气相沉积来沉积中间线衬里。 通过使用等离子体增强化学气相沉积，可以根据核心区域和外围区域中的晶体管之间的距离来控制沉积在芯区域和外围区域中的MOL衬垫的量。

公开(公告)号：US06740568B2

公开(公告)日：2004-05-25

申请号：US10206875

申请日：2002-07-29

Applicant: Yun Yu Wang ,  Johnathan Faltermeier ,  Colleen M. Snavely ,  Michael Maldei ,  Michael M. Iwatake ,  David M. Dobuzinsky ,  Ravikumar Ramachandran ,  Viraj Y. Sardesai ,  Philip L. Flaitz ,  Lisa Y. Ninomiya

Inventor： Yun Yu Wang ,  Johnathan Faltermeier ,  Colleen M. Snavely ,  Michael Maldei ,  Michael M. Iwatake ,  David M. Dobuzinsky ,  Ravikumar Ramachandran ,  Viraj Y. Sardesai ,  Philip L. Flaitz ,  Lisa Y. Ninomiya

IPC: H01L2136

CPC classification number: H01L21/02667 ,  H01L21/02046 ,  H01L21/02532 ,  H01L21/2022 ,  H01L21/28525 ,  H01L27/10873

Abstract: In a method of forming a contact, a liner reactive ion etch is affected on a substrate to remove silicon nitride and silicon oxide. An oxygen plasma ex-situ clean, a Huang AB clean, and a dilute hydrofluric acid (DHF) clean are affected. Amorphous silicon is deposited and an anneal is performed to regrow and recrystallize amorphous silicon.

Abstract translation: 在形成接触的方法中，在衬底上影响衬里反应离子蚀刻以去除氮化硅和氧化硅。 氧等离子体原位清洗，黄AB清洁剂和稀释的氢氟酸（DHF）清洁剂都受到影响。 沉积非晶硅并进行退火以再结晶并重结晶非晶硅。

公开(公告)号：US08606982B2

公开(公告)日：2013-12-10

申请号：US12045369

申请日：2008-03-10

Applicant: Michael Maldei ,  Petra Stumm

Inventor： Michael Maldei ,  Petra Stumm

IPC: G06F13/14

CPC classification number: G06F13/4217 ,  Y02D10/14 ,  Y02D10/151

Abstract: Embodiments of the invention are related to methods, systems, and articles of manufacture for transferring data between two devices using an interconnect bus. On each conductive line of the bus, a bit representing a first logic state is transferred if a current bit is the same as an immediately previously transmitted bit. If the current bit is different from the immediately previously transmitted bit, then a bit representing a second logic state is transferred.

Abstract translation: 本发明的实施例涉及使用互连总线在两个设备之间传送数据的方法，系统和制品。 在总线的每个导线上，如果当前位与之前发送的位相同，则传送表示第一逻辑状态的位。 如果当前位不同于紧接在先发送的位，则传送表示第二逻辑状态的位。

公开(公告)号：US06909152B2

公开(公告)日：2005-06-21

申请号：US10294329

申请日：2002-11-14

Applicant: Michael Maldei ,  Brian Cousineau ,  Guenter Gerstmeier ,  Jon S. Berry, II ,  Steven M. Baker ,  Jinhwan Lee

Inventor： Michael Maldei ,  Brian Cousineau ,  Guenter Gerstmeier ,  Jon S. Berry, II ,  Steven M. Baker ,  Jinhwan Lee

IPC: H01L21/336 ,  H01L21/82 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/10 ,  H01L29/40 ,  H01L29/739 ,  H01L29/76 ,  H01L29/78

CPC classification number: H01L27/10894 ,  H01L27/10873

Abstract: A dynamic random access memory (DRAM) structure having a distance less than 0.14 μm between the contacts to silicon and the gate conductor is disclosed. In addition a method for forming the structure is disclosed, which includes forming the DRAM array contacts and the contacts to silicon simultaneously.

Abstract translation: 公开了一种在硅与栅极导体的触点之间具有小于0.14μm的距离的动态随机存取存储器（DRAM）结构。 此外，公开了一种用于形成结构的方法，其包括同时形成DRAM阵列触点和与硅的触点。

公开(公告)号：US06890815B2

公开(公告)日：2005-05-10

申请号：US10655199

申请日：2003-09-04

Applicant: Johnathan Faltermeier ,  Jeremy Stephens ,  David Dobuzinsky ,  Larry Clevenger ,  Munir D. Naeem ,  Chienfan Yu ,  Larry Nesbit ,  Rama Divakaruni ,  Michael Maldei

Inventor： Johnathan Faltermeier ,  Jeremy Stephens ,  David Dobuzinsky ,  Larry Clevenger ,  Munir D. Naeem ,  Chienfan Yu ,  Larry Nesbit ,  Rama Divakaruni ,  Michael Maldei

IPC: H01L21/60 ,  H01L21/8242 ,  H01L29/76

CPC classification number: H01L27/10888 ,  H01L21/76897 ,  H01L27/10864 ,  H01L27/10876 ,  H01L27/10891

Abstract: A method of forming borderless contacts and a borderless contact structure for semiconductor devices. A preferred embodiment comprises using a second etch selectivity material disposed over a first etch selectivity material to preserve the first etch selectivity material during the etch processes for the various material layers of the semiconductor device while forming the borderless contacts.

Abstract translation: 形成无边界接触的方法和用于半导体器件的无边界接触结构。 优选实施例包括使用设置在第一蚀刻选择性材料上的第二蚀刻选择性材料，以在半导体器件的各种材料层的蚀刻工艺期间保持第一蚀刻选择性材料，同时形成无边界接触。

公开(公告)号：US20050062111A1

公开(公告)日：2005-03-24

申请号：US10960735

申请日：2004-10-07

Applicant: Michael Maldei ,  Jinhwan Lee ,  Guenter Gerstmeier ,  Brian Cousineau ,  Jon Berry ,  Steven Baker ,  Malati Hedge

Inventor： Michael Maldei ,  Jinhwan Lee ,  Guenter Gerstmeier ,  Brian Cousineau ,  Jon Berry ,  Steven Baker ,  Malati Hedge

IPC: H01L21/318 ,  H01L21/8239 ,  H01L21/8242 ,  H01L27/105 ,  H01L27/148 ,  H01L29/76

CPC classification number: H01L27/1052 ,  H01L21/3185 ,  H01L27/105 ,  H01L27/10876 ,  H01L27/10891 ,  H01L27/10894

Abstract: A process for fabricating a semiconductor structure, wherein the semiconductor structure includes a core region and a periphery region. The core region includes a plurality of transistors and the periphery region includes a plurality of transistors. The process includes depositing a middle-of-line liner using plasma enhanced chemical vapor deposition overlying the semiconductor structure. By using a plasma enhanced chemical vapor deposition the amount of MOL liner deposited in the core region and the periphery region can be controlled depending on the distances between transistors in the core region and periphery region.

Abstract translation: 一种制造半导体结构的方法，其中半导体结构包括芯区域和周边区域。 芯区域包括多个晶体管，并且周边区域包括多个晶体管。 该方法包括使用覆盖半导体结构的等离子体增强化学气相沉积来沉积中间线衬里。 通过使用等离子体增强化学气相沉积，可以根据核心区域和外围区域中的晶体管之间的距离来控制沉积在芯区域和外围区域中的MOL衬垫的量。

公开(公告)号：US20050014332A1

公开(公告)日：2005-01-20

申请号：US10619884

申请日：2003-07-15

Applicant: Michael Maldei ,  Johnathan Faltermeier ,  David Dobuzinsky ,  Prakash Dev ,  Thomas Rupp

Inventor： Michael Maldei ,  Johnathan Faltermeier ,  David Dobuzinsky ,  Prakash Dev ,  Thomas Rupp

IPC: H01L21/302 ,  H01L21/336 ,  H01L21/461 ,  H01L21/768 ,  H01L21/8242

CPC classification number: H01L21/76895 ,  H01L27/10864 ,  H01L27/10888

Abstract: A semiconductor device is fabricated to have improved bitline contact formation. Polysilicon is deposited between gate contacts that connect to transistors of DRAM memory cells. The polysilicon covers the gate contacts and continues to cover the gate contacts during subsequent processing steps. A bitline of, e.g., tungsten, is deposited so that it contacts at least a portion of the polysilicon, thereby providing electrical contact with the DRAM transistors.

Abstract translation: 制造半导体器件具有改进的位线接触形成。 多晶硅沉积在连接到DRAM存储单元的晶体管的栅极触点之间。 多晶硅覆盖栅极触点，并在后续处理步骤中继续覆盖栅极触点。 沉积例如钨的位线，使得其接触多晶硅的至少一部分，由此提供与DRAM晶体管的电接触。