公开(公告)号：US08455859B2

公开(公告)日：2013-06-04

申请号：US12571604

申请日：2009-10-01

申请人： Ming-Huan Tsai ,  Han-Ting Tsai

发明人： Ming-Huan Tsai ,  Han-Ting Tsai

IPC分类号： H01L29/06 ,  H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109

CPC分类号： H01L21/823418 ,  H01L21/8238 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/165 ,  H01L29/66477 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/7833 ,  H01L29/7848

摘要： The present disclosure provides a semiconductor device that includes a semiconductor substrate, a gate structure disposed on a surface of the substrate, and strained structures disposed in the substrate at either side of the gate structure and formed of a semiconductor material different from the semiconductor substrate. Each strained structure has a cross-sectional profile that includes a first portion that extends from the surface of substrate and a second portion that tapers from the first portion at an angle ranging from about 50° to about 70°. The angle is measured with respect to an axis parallel to the surface of the substrate.

摘要翻译： 本公开提供一种半导体器件，其包括半导体衬底，设置在衬底的表面上的栅极结构以及设置在栅极结构的任一侧的衬底中的应变结构，并且由与半导体衬底不同的半导体材料形成。 每个应变结构具有横截面轮廓，该截面轮廓包括从基底表面延伸的第一部分和从第一部分以约50°至约70°的角度逐渐变细的第二部分。 角度相对于平行于基板表面的轴线被测量。

公开(公告)号：US08405160B2

公开(公告)日：2013-03-26

申请号：US12787972

申请日：2010-05-26

申请人： Chun-Fai Cheng ,  Fung Ka Hing ,  Ming-Huan Tsai ,  Chun-Feng Nieh ,  Yimin Huang ,  Han-Ting Tsai ,  Haiting Wang

发明人： Chun-Fai Cheng ,  Fung Ka Hing ,  Ming-Huan Tsai ,  Chun-Feng Nieh ,  Yimin Huang ,  Han-Ting Tsai ,  Haiting Wang

IPC分类号： H01L27/088 ,  H01L21/8238

CPC分类号： H01L29/7848 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/30608 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833

摘要： The present disclosure provides a semiconductor device. The semiconductor device includes a silicon substrate. The semiconductor device includes first and second regions that are disposed in the substrate. The first and second regions have a silicon compound material. The semiconductor device includes first and second source/drain structures that are partially disposed in the first and second regions, respectively. The semiconductor device includes a first gate that is disposed over the substrate. The first gate has a first proximity to the first region. The semiconductor device includes a second gate that is disposed over the substrate. The second gate has a second proximity to the second region. The second proximity is different from the first proximity. The first source/drain structure and the first gate are portions of a first transistor, and the second source/drain structure and the second gate are portions of a second transistor.

摘要翻译： 本发明提供一种半导体器件。 半导体器件包括硅衬底。 半导体器件包括设置在衬底中的第一和第二区域。 第一和第二区域具有硅化合物材料。 半导体器件包括分别部分地设置在第一和第二区域中的第一和第二源极/漏极结构。 半导体器件包括设置在衬底上的第一栅极。 第一个门第一个靠近第一个地区。 半导体器件包括设置在衬底上的第二栅极。 第二个门第二个靠近第二个区域。 第二接近度与第一接近度不同。 第一源极/漏极结构和第一栅极是第一晶体管的部分，并且第二源极/漏极结构和第二栅极是第二晶体管的部分。

公开(公告)号：US20120273847A1

公开(公告)日：2012-11-01

申请号：US13543943

申请日：2012-07-09

申请人： Ming-Huan Tsai ,  Hui Ouyang ,  Chun-Fai Cheng ,  Wei-Han Fan

发明人： Ming-Huan Tsai ,  Hui Ouyang ,  Chun-Fai Cheng ,  Wei-Han Fan

IPC分类号： H01L27/085

CPC分类号： H01L21/823807 ,  H01L21/02433 ,  H01L21/02639 ,  H01L21/823814 ,  H01L29/7848

摘要： An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved control over a surface proximity and tip depth of integrated circuit devices. An exemplary integrated circuit device achieved by the method has a surface proximity of about 1 nm to about 3 nm and a tip depth of about 5 nm to about 10 nm. The integrated circuit device having such surface proximity and tip depth includes an epi source feature and an epi drain feature defined by a first facet and a second facet of a substrate in a first direction, such as a {111} crystallographic plane of the substrate, and a third facet of the substrate in a second direction, such as a { 100} crystallographic plane of the substrate.

摘要翻译： 公开了一种用于制造集成电路器件的集成电路器件和方法。 所公开的方法提供对集成电路器件的表面接近度和尖端深度的改进的控制。 通过该方法实现的示例性集成电路器件具有约1nm至约3nm的表面接近度和约5nm至约10nm的尖端深度。 具有这种表面接近度和尖端深度的集成电路器件包括由第一方向（例如衬底的{111}晶体平面）的第一方向上的第一面和第二小面限定的外延源特征和外延漏极特征， 以及在第二方向上的衬底的第三面，例如衬底的{100}晶面。

公开(公告)号：US20110312145A1

公开(公告)日：2011-12-22

申请号：US12816519

申请日：2010-06-16

申请人： Ming-Huan Tsai ,  Chun-Fai Cheng ,  Hui Ouyang ,  Yuan-Hung Chiu ,  Yen-Ming Chen

发明人： Ming-Huan Tsai ,  Chun-Fai Cheng ,  Hui Ouyang ,  Yuan-Hung Chiu ,  Yen-Ming Chen

IPC分类号： H01L21/336

CPC分类号： H01L29/66515 ,  H01L21/265 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

摘要： An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved control over a surface proximity and tip depth of integrated circuit device. In an embodiment, the method achieves improved control by forming a doped region and a lightly doped source and drain (LDD) region in a source and drain region of the device. The doped region is implanted with a dopant type opposite the LDD region.

摘要翻译： 公开了一种用于制造集成电路器件的集成电路器件和方法。 所公开的方法提供对集成电路器件的表面接近度和尖端深度的改进的控制。 在一个实施例中，该方法通过在器件的源极和漏极区域中形成掺杂区域和轻掺杂源极和漏极（LDD）区域来实现改进的控制。 掺杂区域注入与LDD区域相反的掺杂剂类型。

公开(公告)号：US20110254105A1

公开(公告)日：2011-10-20

申请号：US12761949

申请日：2010-04-16

申请人： Chun-Fai Cheng ,  Ka-Hing Fung ,  Han-Ting Tsai ,  Ming-Huan Tsai ,  Wei-Han Fan ,  Hsueh-Chang Sung ,  Haiting Wang ,  Wei-Yuan Lu ,  Hsien-Ching Lo ,  Kuan-Chung Chen

发明人： Chun-Fai Cheng ,  Ka-Hing Fung ,  Han-Ting Tsai ,  Ming-Huan Tsai ,  Wei-Han Fan ,  Hsueh-Chang Sung ,  Haiting Wang ,  Wei-Yuan Lu ,  Hsien-Ching Lo ,  Kuan-Chung Chen

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66636 ,  H01L21/28518 ,  H01L21/30608 ,  H01L21/3065 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/66628 ,  H01L29/7834 ,  H01L29/7848

摘要： A semiconductor device having a strained channel and a method of manufacture thereof is provided. The semiconductor device has a gate electrode formed over a channel recess. A first recess and a second recess formed on opposing sides of the gate electrode are filled with a stress-inducing material. The stress-inducing material extends into an area wherein source/drain extensions overlap an edge of the gate electrode. In an embodiment, sidewalls of the channel recess and/or the first and second recesses may be along {111} facet planes.

摘要翻译： 提供了具有应变通道的半导体器件及其制造方法。 半导体器件具有形成在通道凹槽上的栅电极。 形成在栅电极的相对侧上的第一凹部和第二凹部填充有应力诱导材料。 应力诱导材料延伸到其中源极/漏极延伸部与栅电极的边缘重叠的区域中。 在一个实施例中，通道凹槽和/或第一和第二凹部的侧壁可以沿{111}面平面。

公开(公告)号：US20110079856A1

公开(公告)日：2011-04-07

申请号：US12571604

申请日：2009-10-01

申请人： Ming-Huan Tsai ,  Han-Ting Tsai

发明人： Ming-Huan Tsai ,  Han-Ting Tsai

IPC分类号： H01L27/092 ,  H01L29/78

CPC分类号： H01L21/823418 ,  H01L21/8238 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/165 ,  H01L29/66477 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/7833 ,  H01L29/7848

摘要： The present disclosure provides a semiconductor device that includes a semiconductor substrate, a gate structure disposed on a surface of the substrate, and strained structures disposed in the substrate at either side of the gate structure and formed of a semiconductor material different from the semiconductor substrate. Each strained structure has a cross-sectional profile that includes a first portion that extends from the surface of substrate and a second portion that tapers from the first portion at an angle ranging from about 50° to about 70°. The angle is measured with respect to an axis parallel to the surface of the substrate.

摘要翻译： 本公开提供一种半导体器件，其包括半导体衬底，设置在衬底的表面上的栅极结构以及设置在栅极结构的任一侧的衬底中的应变结构，并且由与半导体衬底不同的半导体材料形成。 每个应变结构具有横截面轮廓，该截面轮廓包括从基底表面延伸的第一部分和从第一部分以约50°至约70°的角度逐渐变细的第二部分。 角度相对于平行于基板表面的轴线被测量。

公开(公告)号：US20070040188A1

公开(公告)日：2007-02-22

申请号：US11207450

申请日：2005-08-19

申请人： Ming-Huan Tsai ,  Fang-Cheng Chen ,  Chao-Cheng Chen ,  Syun-Ming Jang

发明人： Ming-Huan Tsai ,  Fang-Cheng Chen ,  Chao-Cheng Chen ,  Syun-Ming Jang

IPC分类号： H01L31/00

CPC分类号： H01L21/76897 ,  H01L21/76804 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit chip includes a buffer layer, an underlying layer, a dielectric layer, a hole, and barrier layer. The buffer layer is over the underlying layer. The dielectric layer is over the buffer layer. The hole is formed in and extending through the dielectric layer and the buffer layer, and opens to the underlying layer. The hole includes a buffer layer portion at the buffer layer and a dielectric layer portion at the dielectric layer. At least part of the buffer layer portion of the hole has a larger cross-section area than a smallest cross-section area of the dielectric layer portion of the hole. The conformal barrier layer covers surfaces of the dielectric layer and the buffer layer in the hole. The hole is a via hole or a contact hole that is later filled with a conductive material to form a conductive via or a conductive contact.

摘要翻译： 集成电路芯片包括缓冲层，下层，电介质层，空穴和阻挡层。 缓冲层位于底层之上。 电介质层在缓冲层之上。 孔形成并延伸穿过介电层和缓冲层，并向下层开放。 该孔包括在缓冲层处的缓冲层部分和介电层处的电介质层部分。 孔的缓冲层部分的至少一部分具有比孔的电介质层部分的最小横截面面积更大的横截面面积。 保形阻挡层覆盖孔中的介电层和缓冲层的表面。 孔是通孔或接触孔，其后面填充有导电材料以形成导电通孔或导电接触。

公开(公告)号：US07078351B2

公开(公告)日：2006-07-18

申请号：US10361875

申请日：2003-02-10

申请人： Yuan-Hung Chiu ,  Ming-Huan Tsai ,  Hun-Jan Tao ,  Jeng-Horng Chen

发明人： Yuan-Hung Chiu ,  Ming-Huan Tsai ,  Hun-Jan Tao ,  Jeng-Horng Chen

IPC分类号： H01L21/302

CPC分类号： H01L21/0276 ,  H01L21/0332 ,  H01L21/30604 ,  H01L21/3081 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/3144 ,  H01L21/3145 ,  H01L21/76802

摘要： A layer of Anti Reflective Coating (ARC) is first deposited over the surface of a silicon based or oxide based semiconductor surface, a dual hardmask is deposited over the surface of the layer of ARC. A layer of soft mask material is next coated over the surface of the dual hardmask layer, the layer of soft mask material is exposed, creating a soft mask material mask. The upper layer of the dual hardmask layer is next patterned in accordance with the soft mask material mask, the soft mask material mask is removed from the surface. The lower layer of the hardmask layer is then patterned after which the layer of ARC is patterned, both layers are patterned in accordance with the patterned upper layer of the dual hardmask layer. The substrate is now patterned in accordance with the patterned upper and lower layer of the dual hardmask layer and the patterned layer of ARC. The patterned upper and lower layers of the hardmask layer and the patterned layer of ARC are removed from the surface of the silicon based or oxide based semiconductor surface.

摘要翻译： 首先将抗反射涂层（ARC）沉积在硅基或氧化物基半导体表面的表面上，双重硬掩模沉积在ARC层的表面上。 然后将一层软掩模材料涂覆在双重硬掩模层的表面上，该软掩模材料层被暴露，形成柔软的掩模材料掩模。 根据软掩模材料掩模，双硬掩模层的上层接下来图案化，从表面去除软掩模材料掩模。 然后对硬掩模层的下层进行图案化，之后对ARC层进行构图，根据双重硬掩模层的图案化上层对两层进行图案化。 衬底现在根据双重硬掩模层的图案化的上下层和ARC的图案化层进行图案化。 从硅基或氧化物基半导体表面的表面去除硬掩模层的图案化的上层和下层以及ARC的图案化层。

公开(公告)号：US20060099745A1

公开(公告)日：2006-05-11

申请号：US10981925

申请日：2004-11-05

申请人： Ju-Wang Hsu ,  Ming-Huan Tsai ,  Chien-Hao Chen ,  Yi-Chun Huang

发明人： Ju-Wang Hsu ,  Ming-Huan Tsai ,  Chien-Hao Chen ,  Yi-Chun Huang

IPC分类号： H01L21/84 ,  H01L21/00

CPC分类号： H01L29/7842 ,  H01L21/823807 ,  H01L21/823835 ,  H01L21/823864 ,  H01L21/823878 ,  H01L29/7843 ,  Y10S438/938

摘要： An integrated advanced method for forming a semiconductor device utilizes a sacrificial stress layer as part of a film stack that enables spatially selective silicide formation in the device. The low-resistance portion of the device to be silicided includes NMOS transistors and PMOS transistors. The stressed film may be a tensile or compressive nitride film. An annealing process is carried out prior to the silicide formation process. During the annealing process, the stressed nitride film preferentially remains over either the NMOS transistors or PMOS transistors, but not both, to optimize device performance. A tensile nitride film remains over the NMOS transistors but not the PMOS transistors while a compressive nitride film remains over the PMOS transistors but not the NMOS transistors, during anneal.

摘要翻译： 用于形成半导体器件的集成先进方法利用牺牲应力层作为薄膜堆叠的一部分，其能够在器件中形成空间选择性硅化物。 要被硅化的器件的低电阻部分包括NMOS晶体管和PMOS晶体管。 应力膜可以是拉伸或压缩氮化物膜。 在硅化物形成工艺之前进行退火处理。 在退火过程中，应力氮化物膜优先保留在NMOS晶体管或PMOS晶体管之上，但不能同时保持在两者上，以优化器件性能。 在退火期间，拉伸氮化物膜保留在NMOS晶体管上，而不是PMOS晶体管，而压电氮化物膜保留在PMOS晶体管上，而不保留在NMOS晶体管上。

公开(公告)号：US20060086690A1

公开(公告)日：2006-04-27

申请号：US10971265

申请日：2004-10-21

申请人： Ming-Huan Tsai ,  Fong-Yuh Yen ,  Hun-Jan Tao

发明人： Ming-Huan Tsai ,  Fong-Yuh Yen ,  Hun-Jan Tao

IPC分类号： C23F1/00 ,  C03C25/68 ,  B44C1/22

CPC分类号： H01L21/31116

摘要： A method of dry etching a dielectric layer is provided that prevents or significantly reduces deep ultraviolet photoresist damage and bird's beak problems. The dry etch method provided comprises the steps of providing a substrate having a dielectric layer overlying at least a portion of the substrate's surface; applying a deep ultraviolet (DUV) photoresist mask having a pattern of exposed area on at least a portion of the dielectric layer; and etching the masked dielectric layer with a plasma formed from a mixture of gases comprising a gaseous fluorine species, hydrogen, and helium.

摘要翻译： 提供了干蚀刻电介质层的方法，其防止或显着降低深紫外光致抗蚀剂损伤和鸟嘴问题。 所提供的干蚀刻方法包括以下步骤：提供具有覆盖在基底表面的至少一部分上的介电层的基底; 在所述电介质层的至少一部分上施加具有暴露区域图案的深紫外（DUV）光致抗蚀剂掩模; 并用由包含气态氟物质，氢气和氦气的气体混合物形成的等离子体蚀刻掩蔽的电介质层。