摘要:
An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved control over a surface proximity and tip depth of integrated circuit device. In an embodiment, the method achieves improved control by forming a doped region and a lightly doped source and drain (LDD) region in a source and drain region of the device. The doped region is implanted with a dopant type opposite the LDD region.
摘要:
An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved control over a surface proximity and tip depth of integrated circuit device. In an embodiment, the method achieves improved control by forming a doped region and a lightly doped source and drain (LDD) region in a source and drain region of the device. The doped region is implanted with a dopant type opposite the LDD region.
摘要:
An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved control over a surface proximity and tip depth of integrated circuit device. In an embodiment, the method achieves improved control by forming a doped region and a lightly doped source and drain (LDD) region in a source and drain region of the device. The doped region is implanted with a dopant type opposite the LDD region.
摘要:
An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved control over a surface proximity and tip depth of integrated circuit device. In an embodiment, the method achieves improved control by forming a doped region and a lightly doped source and drain (LDD) region in a source and drain region of the device. The doped region is implanted with a dopant type opposite the LDD region.
摘要:
A field effect transistor gate structure and a method of fabricating the gate structure with a high-k gate dielectric material and high-k spacer are described. A gate pattern or trench is first etched in a dummy organic or inorganic film deposited over a silicon substrate with source/drain regions. A high-k dielectric material liner is then deposited on all exposed surfaces. Excess poly-silicon gate conductor film is then deposited within and over the trench to provide adequate overburden. Poly-silicon is then planarized with chemical mechanical polishing or etch-back methods such that the high-k material film on top of the dummy film surface is removed during this step. In the final step, the dummy film is disposed off, leaving the final transistor gate structure with high-k gate dielectric and high-k spacer surrounding the gate conductor poly-silicon, with the entire gate structure fabricated to form an FET device on a silicon substrate.
摘要:
The present invention provides aqueous compositions for cleaning integrated circuit substrates. Specifically, in the cleaning of an integrated circuit substrate, disclosed is a method for removing the by-products of the high-k dielectric dry etch process from the integrated circuit substrate, the method including: contacting the integrated circuit substrate with an aqueous composition including an amount, effective for the purpose of a (a) hydrogen fluoride, followed by (b) a mixture of hydrogen peroxide with a compound selected from the group consisting of ammonium hydroxide, hydrochloric acid and sulfuric acid.
摘要:
A fully dry etch method is described for removing a high k dielectric layer from a substrate without damaging the substrate and has a high selectivity with respect to a gate layer. The etch is comprised of BCl3, a fluorocarbon, and an inert gas. A low RF bias power is preferred. The method can also be used to remove an interfacial layer between the substrate and the high k dielectric layer. A HfO2 etch rate of 55 Angstroms per minute is achieved without causing a recess in a silicon substrate and with an etch selectivity to polysilicon of greater than 10:1. Better STI oxide divot control is also provided by this method. The etch through the high k dielectric layer may be performed in the same etch chamber as the etch process to form a gate electrode.
摘要:
A field effect transistor gate structure and a method of fabricating the gate structure with a high-k gate dielectric material and high-k spacer are described. A gate pattern or trench is first etched in a dummy organic or inorganic film deposited over a silicon substrate with source/drain regions. A high-k dielectric material liner is then deposited on all exposed surfaces. Excess poly-silicon gate conductor film is then deposited within and over the trench to provide adequate overburden. Poly-silicon is then planarized with chemical mechanical polishing or etch-back methods such that the high-k material film on top of the dummy film surface is removed during this step. In the final step, the dummy film is disposed off, leaving the final transistor gate structure with high-k gate dielectric and high-k spacer surrounding the gate conductor poly-silicon, with the entire gate structure fabricated to form an FET device on a silicon substrate.
摘要:
A method of manufacturing a semiconductor device is provided. A semiconductor element is formed on a substrate. The semiconductor element has at least one nickel silicide contact region, an etch stop layer formed over said element, and an insulating layer formed over said etch stop layer. A portion of the etch stop layer immediately over a selected contact region is removed using a process that does not substantially react with the contact region, to form a contact opening. The contact opening is then filled with a conductive material to form a contact.
摘要:
A layer of Anti Reflective Coating (ARC) is first deposited over the surface of a silicon based or oxide based semiconductor surface, a dual hardmask is deposited over the surface of the layer of ARC. A layer of soft mask material is next coated over the surface of the dual hardmask layer, the layer of soft mask material is exposed, creating a soft mask material mask. The upper layer of the dual hardmask layer is next patterned in accordance with the soft mask material mask, the soft mask material mask is removed from the surface. The lower layer of the hardmask layer is then patterned after which the layer of ARC is patterned, both layers are patterned in accordance with the patterned upper layer of the dual hardmask layer. The substrate is now patterned in accordance with the patterned upper and lower layer of the dual hardmask layer and the patterned layer of ARC. The patterned upper and lower layers of the hardmask layer and the patterned layer of ARC are removed from the surface of the silicon based or oxide based semiconductor surface.