公开(公告)号：US20070064464A1

公开(公告)日：2007-03-22

申请号：US11229527

申请日：2005-09-20

Applicant: Tiao-Hua Kuo ,  Nancy Leong ,  Nian Yang ,  Guowei Wang ,  Aaron Lee ,  Sachit Chandra ,  Michael VanBuskirk ,  Johnny Chen ,  Darlene Hamilton ,  Binh Le

Inventor： Tiao-Hua Kuo ,  Nancy Leong ,  Nian Yang ,  Guowei Wang ,  Aaron Lee ,  Sachit Chandra ,  Michael VanBuskirk ,  Johnny Chen ,  Darlene Hamilton ,  Binh Le

IPC: G11C17/00

CPC classification number: G11C5/147 ,  G11C16/12

Abstract: A method is provided for programming a nonvolatile memory array including an array of memory cells, where each memory cell including a substrate, a control gate, a charge storage element, a source region and a drain region. The method includes receiving a programming window containing a predetermined number of bits that are to be programmed in the array and determining which of the predetermined number of bits are to be programmed in the memory array. The predetermined number of bits are simultaneously programmed to corresponding memory cells in the array. A programming state of the predetermined number of bits in the array is simultaneously verified.

Abstract translation: 提供了一种用于对包括存储器单元阵列的非易失性存储器阵列进行编程的方法，其中每个存储单元包括衬底，控制栅极，电荷存储元件，源极区域和漏极区域。 该方法包括接收包含要在阵列中被编程的预定数量的位的编程窗口，并且确定在存储器阵列中哪个预定位数被编程。 预定数量的位同时被编程到阵列中的对应存储器单元。 同时验证阵列中预定位数的编程状态。

公开(公告)号：US20070035991A1

公开(公告)日：2007-02-15

申请号：US11189923

申请日：2005-07-27

Applicant: Hounien Chen ,  Nancy Leong

Inventor： Hounien Chen ,  Nancy Leong

IPC: G11C16/04

CPC classification number: G11C16/26

Abstract: A method for reading a nonvolatile memory array including an array of memory cells, each memory cell including a substrate, a control gate, a charge storage element, a source region and a drain region, includes receiving, at an address register, a read command including an address for a memory cell in the array of memory cells and an indication regarding whether the read command is a full page read command or a partial page read command. A starting address for a page including the received address is identified, wherein the page includes multiple rows of memory cells in the array of memory cells. The address register is reset to the starting address for the page. It is determined whether all memory cells in the page are non-programmed. Data indicative of a non-programmed state of the page is output if it is determined that all memory cells in the page are non-programmed.

Abstract translation: 一种用于读取包括存储器单元阵列的非易失性存储器阵列的方法，每个存储单元包括衬底，控制栅极，电荷存储元件，源极区域和漏极区域，包括在地址寄存器处接收读取命令 包括存储器单元阵列中的存储器单元的地址以及关于读取命令是全页读取命令还是部分页面读取命令的指示。 识别包括接收到的地址的页面的起始地址，其中页面包括存储器单元阵列中的多行存储器单元。 地址寄存器将重置为页面的起始地址。 确定页面中的所有存储单元是否被编程。 如果确定页面中的所有存储器单元都未被编程，则输出指示页面的非编程状态的数据。

公开(公告)号：US6157567A

公开(公告)日：2000-12-05

申请号：US70160

申请日：1998-04-30

Applicant: Tiao-Hua Kuo ,  Eric Itakura ,  May Xie ,  Nancy Leong

Inventor： Tiao-Hua Kuo ,  Eric Itakura ,  May Xie ,  Nancy Leong

IPC: G11C16/10 ,  G11C16/04

CPC classification number: G11C16/10

Abstract: The invention is directed to a single power supply pin non-volatile memory device that increases programming speed by providing for two-cycle programming. The invention maintains measures to prevent accidental user overwrites and maintains JEDEC standard compatibility. To provide for two-cycle programming, a three-cycle unlock bypass command is first sent, in one embodiment, after which a plurality of consecutive two-cycle program commands can be sent.

Abstract translation: 本发明涉及通过提供两周期编程来提高编程速度的单个电源引脚非易失性存储器件。 本发明保持措施以防止意外用户重写并维护JEDEC标准的兼容性。 为了提供双周期编程，首先发送三周期解锁旁路命令，在一个实施例中，之后可以发送多个连续的两周期程序命令。

公开(公告)号：US20120294103A1

公开(公告)日：2012-11-22

申请号：US13569442

申请日：2012-08-08

Applicant: Sung-Yong Chung ,  Zhizheng Liu ,  Yugi Mizuguchi ,  Xuguang Alan Wang ,  Yi He ,  Ming Kwan ,  Darlene Hamilton ,  Sung-Chul Lee ,  Guowei Wang ,  Nancy Leong

Inventor： Sung-Yong Chung ,  Zhizheng Liu ,  Yugi Mizuguchi ,  Xuguang Alan Wang ,  Yi He ,  Ming Kwan ,  Darlene Hamilton ,  Sung-Chul Lee ,  Guowei Wang ,  Nancy Leong

IPC: G11C7/12

CPC classification number: G11C16/3418 ,  G11C16/0416 ,  G11C16/24 ,  G11C16/3427

Abstract: A system and methodology that can minimize disturbance during an AC operation associated with a memory, such as, program, read and/or erase, is provided. The system pre-charges all or a desired subset of the bit lines in a memory array to a specified voltage, during an AC operation to facilitate reducing AC disturbances between neighboring cells. A pre-charge voltage can be applied to all bit lines in a block in the memory array, or to bit lines associated with a selected memory cell and neighbor memory cells adjacent to the selected memory cell in the block. The system ensures that source and drain voltage levels can be set to desired levels at the same or substantially the same time, while selecting a memory cell. This can facilitate minimizing AC disturbances in the selected memory cell during the AC operation.

Abstract translation: 提供了一种能够在与诸如程序，读取和/或擦除之类的存储器相关联的AC操作期间最小化干扰的系统和方法。 在AC操作期间，系统将存储器阵列中的所有或所需的位线子集预充电到指定的电压，以便于减少相邻单元之间的AC干扰。 可以将预充电电压施加到存储器阵列中的块中的所有位线，或者对与所选择的存储器单元相关联的位线以及与块中所选择的存储单元相邻的相邻存储单元。 该系统确保在选择存储器单元时，源极和漏极电压电平可以在相同或基本相同的时间被设置为期望的电平。 这可以有助于在AC操作期间最小化所选择的存储器单元中的AC干扰。

公开(公告)号：US07679967B2

公开(公告)日：2010-03-16

申请号：US11963508

申请日：2007-12-21

Applicant: Sung-Yong Chung ,  Zhizheng Liu ,  Yugi Mizuguchi ,  Xuguang Alan Wang ,  Yi He ,  Ming Kwan ,  Darlene Hamilton ,  Sung-Chul Lee ,  Guowei Wang ,  Nancy Leong

Inventor： Sung-Yong Chung ,  Zhizheng Liu ,  Yugi Mizuguchi ,  Xuguang Alan Wang ,  Yi He ,  Ming Kwan ,  Darlene Hamilton ,  Sung-Chul Lee ,  Guowei Wang ,  Nancy Leong

IPC: G11C16/06

CPC classification number: G11C16/3418 ,  G11C16/0416 ,  G11C16/24 ,  G11C16/3427

Abstract: A system and methodology that can minimize disturbance during an AC operation associated with a memory, such as, program, read and/or erase, is provided. The system pre-charges all or a desired subset of the bit lines in a memory array to a specified voltage, during an AC operation to facilitate reducing AC disturbances between neighboring cells. A pre-charge voltage can be applied to all bit lines in a block in the memory array, or to bit lines associated with a selected memory cell and neighbor memory cells adjacent to the selected memory cell in the block. The system ensures that source and drain voltage levels can be set to desired levels at the same or substantially the same time, while selecting a memory cell. This can facilitate minimizing AC disturbances in the selected memory cell during the AC operation.

Abstract translation: 提供了一种能够在与诸如程序，读取和/或擦除之类的存储器相关联的AC操作期间最小化干扰的系统和方法。 在AC操作期间，系统将存储器阵列中的所有或所需的位线子集预充电到指定的电压，以便于减少相邻单元之间的AC干扰。 可以将预充电电压施加到存储器阵列中的块中的所有位线，或者对与所选择的存储器单元相关联的位线以及与块中所选择的存储单元相邻的相邻存储单元。 该系统确保在选择存储器单元时，源极和漏极电压电平可以在相同或基本相同的时间被设置为期望的电平。 这可以有助于在AC操作期间最小化所选择的存储器单元中的AC干扰。

公开(公告)号：US07443732B2

公开(公告)日：2008-10-28

申请号：US11229527

申请日：2005-09-20

Applicant: Tiao-Hua Kuo ,  Nancy Leong ,  Nian Yang ,  Guowei Wang ,  Aaron Lee ,  Sachit Chandra ,  Michael A. VanBuskirk ,  Johnny Chen ,  Darlene Hamilton ,  Binh Quang Le

Inventor： Tiao-Hua Kuo ,  Nancy Leong ,  Nian Yang ,  Guowei Wang ,  Aaron Lee ,  Sachit Chandra ,  Michael A. VanBuskirk ,  Johnny Chen ,  Darlene Hamilton ,  Binh Quang Le

IPC: G11C11/34

CPC classification number: G11C5/147 ,  G11C16/12

Abstract: A method is provided for programming a nonvolatile memory array including an array of memory cells, where each memory cell including a substrate, a control gate, a charge storage element, a source region and a drain region. The method includes receiving a programming window containing a predetermined number of bits that are to be programmed in the array and determining which of the predetermined number of bits are to be programmed in the memory array. The predetermined number of bits are simultaneously programmed to corresponding memory cells in the array. A programming state of the predetermined number of bits in the array is simultaneously verified.

Abstract translation: 提供了一种用于对包括存储器单元阵列的非易失性存储器阵列进行编程的方法，其中每个存储单元包括衬底，控制栅极，电荷存储元件，源极区域和漏极区域。 该方法包括接收包含要在阵列中被编程的预定数量的位的编程窗口，并且确定在存储器阵列中哪个预定位数被编程。 预定数量的位同时被编程到阵列中的对应存储器单元。 同时验证阵列中预定位数的编程状态。

公开(公告)号：US20080049516A1

公开(公告)日：2008-02-28

申请号：US11931992

申请日：2007-10-31

Applicant: Aaron LEE ,  Hounien CHEN ,  Sachit CHANDRA ,  Nancy LEONG ,  Guowei WANG

Inventor： Aaron LEE ,  Hounien CHEN ,  Sachit CHANDRA ,  Nancy LEONG ,  Guowei WANG

IPC: G11C11/34

CPC classification number: G11C16/0475 ,  G11C16/3454 ,  G11C16/3459

Abstract: A method is provided for programming a nonvolatile memory device including an array of memory cells, where each memory cell including a substrate, a control gate, a charge storage element, a source region and a drain region. The method includes receiving a programming window that identifies a plurality of memory cells in the array. A first group of memory cells to be programmed is identified from the plurality of memory cells in the programming window. The first group of memory cells is programmed and a programming state of the first group of memory cells is verified.

Abstract translation: 提供了一种用于对包括存储器单元阵列的非易失性存储器件进行编程的方法，其中每个存储器单元包括衬底，控制栅极，电荷存储元件，源极区域和漏极区域。 该方法包括接收标识阵列中的多个存储单元的编程窗口。 在编程窗口中从多个存储器单元识别要编程的第一组存储器单元。 第一组存储器单元被编程，并且验证第一组存储器单元的编程状态。

公开(公告)号：US20070064480A1

公开(公告)日：2007-03-22

申请号：US11229519

申请日：2005-09-20

Applicant: Tiao-Hua Kuo ,  Nancy Leong ,  Hounien Chen ,  Sachit Chandra ,  Nian Yang

Inventor： Tiao-Hua Kuo ,  Nancy Leong ,  Hounien Chen ,  Sachit Chandra ,  Nian Yang

IPC: G11C16/04

CPC classification number: G11C16/0491 ,  G11C16/0475 ,  G11C16/10

Abstract: A method is provided for programming a nonvolatile memory array including an array of memory cells, where each memory cell including a substrate, a control gate, a charge storage element having at least two charge storage areas for storing at least two independent charges, a source region and a drain region. The method includes designating at least one memory cell as a high-speed memory cell and pre-conditioning the high-speed memory cells by placing a first of the at least two charge storage areas into a programmed state, and subsequently enabling the programming on the second area with much higher rate.

Abstract translation: 提供了一种用于对包括存储器单元阵列的非易失性存储器阵列进行编程的方法，其中每个存储器单元包括衬底，控制栅极，具有用于存储至少两个独立电荷的至少两个电荷存储区域的电荷存储元件，源 区域和漏极区域。 该方法包括将至少一个存储器单元指定为高速存储单元，并且通过将至少两个电荷存储区域中的第一个置于编程状态来预处理高速存储器单元，并且随后使能在 第二个地区的利率要高得多。

公开(公告)号：US06470414B2

公开(公告)日：2002-10-22

申请号：US09893247

申请日：2001-06-26

Applicant: Tiao-Hua Kuo ,  Yasushi Kasa ,  Nancy Leong ,  Johnny Chen ,  Michael Van Buskirk

Inventor： Tiao-Hua Kuo ,  Yasushi Kasa ,  Nancy Leong ,  Johnny Chen ,  Michael Van Buskirk

IPC: G06F1200

CPC classification number: G11C8/12 ,  G11C16/08

Abstract: A bank selector circuit for a simultaneous operation flash memory device with a flexible bank partition architecture comprises a memory boundary option, a bank selector encoder coupled to receive a memory partition indicator signal from the memory boundary option, and a bank selector decoder coupled to receive a bank selector code from the bank selector encoder. The decoder, upon receiving a memory address, outputs a bank selector output signal to point the memory address to either a lower memory bank or an upper memory bank in the simultaneous operation flash memory device, in dependence upon the selected memory partition boundary.

Abstract translation: 一种用于具有灵活存储区划分架构的同步操作闪速存储器件的存储体选择器电路，包括存储器边界选项，耦合以从存储器边界选项接收存储器分区指示符信号的存储体选择器编码器，以及耦合以接收 来自银行选择器编码器的存储体选择器代码。 解码器在接收到存储器地址时输出存储体选择器输出信号，以根据选择的存储器分区边界将存储器地址指向同时操作闪速存储器件中的下部存储器组或上部存储器组。

公开(公告)号：US06208558B1

公开(公告)日：2001-03-27

申请号：US09293006

申请日：1999-04-16

Applicant: Johnny Chen ,  Tiao-Hua Kuo ,  Nancy Leong

Inventor： Johnny Chen ,  Tiao-Hua Kuo ,  Nancy Leong

IPC: C11C1604

CPC classification number: G11C16/10 ,  G11C16/16

Abstract: An acceleration circuit for fast programming and fast chip erase of a non-volatile memory array (46) comprises an acceleration input (2) coupled to a triggering circuit (4) which is capable of generating fast program and fast chip erase commands. In an embodiment, the triggering circuit (4) comprises a high voltage detector (6), which is coupled to the acceleration input (2), and a logic circuit (8), which is coupled to the high voltage detector (6) and has a plurality of command write inputs (10). In a further embodiment, the acceleration voltage is reduced by a regulator (52) to generate a regulated voltage, which is supplied to the memory cells (72a, 72b, 74a, 74b, . . . ) in fast program and fast chip erase modes.

Abstract translation: 用于非易失性存储器阵列（46）的快速编程和快速芯片擦除的加速电路包括耦合到能够产生快速程序和快速芯片擦除命令的触发电路（4）的加速度输入（2）。 在一个实施例中，触发电路（4）包括耦合到加速输入端（2）的高电压检测器（6）和耦合到高压检测器（6）的逻辑电路（8） 具有多个命令写入输入（10）。 在另一实施例中，通过调节器（52）减小加速电压，以产生以快速程序和快速芯片擦除模式提供给存储单元（72a，72b，74a，74b ...）的调节电压 。