公开(公告)号：US20080263325A1

公开(公告)日：2008-10-23

申请号：US11737491

申请日：2007-04-19

Applicant: Prabhakar Kudva ,  David S. Levitan ,  Balaram Sinharoy ,  John D. Wellman

Inventor： Prabhakar Kudva ,  David S. Levitan ,  Balaram Sinharoy ,  John D. Wellman

IPC: G06F9/30

CPC classification number: G06F9/3851

Abstract: A microprocessor and system with improved performance and power in simultaneous multithreading (SMT) microprocessor architecture. The microprocessor and system includes a process wherein the processor has the ability to select instructions from one thread or another in any given processor clock cycle. Instructions from each, thread may be assigned selection priorities at multiple decision points in a processor in a given cycle dynamically. The thread priority is based on monitoring performance behavior and activities in the processor. In the exemplary embodiment, the present invention discloses a microprocessor and system for synchronizing thread priorities among multiple decision points throughout the micro-architecture of the microprocessor. This system and method for synchronizing thread priorities allows each thread priority to he in sync and aware of the status of other thread priorities at various decision points within the microprocessor.

Abstract translation: 具有同步多线程（SMT）微处理器架构的具有改进的性能和功耗的微处理器和系统。 微处理器和系统包括处理器，其中处理器能够在任何给定的处理器时钟周期中从一个线程或另一个线程中选择指令。 来自每个线程的指令可以在给定周期中的处理器中的多个决策点动态地分配选择优先级。 线程优先级基于监视处理器中的性能行为和活动。 在示例性实施例中，本发明公开了一种微处理器和系统，用于在整个微处理器的微架构中的多个决策点之间同步线程优先级。 这种用于同步线程优先级的系统和方法允许每个线程优先级同步并且在微处理器内的各个决定点处知道其他线程优先级的状态。

公开(公告)号：US20080042140A1

公开(公告)日：2008-02-21

申请号：US11847608

申请日：2007-08-30

Applicant: Syed Alam ,  Ibrahim Elfadel ,  Kathryn Guarini ,  Meikei Ieong ,  Prabhakar Kudva ,  David Kung ,  Mark Lavin ,  Arifur Rahman

Inventor： Syed Alam ,  Ibrahim Elfadel ,  Kathryn Guarini ,  Meikei Ieong ,  Prabhakar Kudva ,  David Kung ,  Mark Lavin ,  Arifur Rahman

IPC: H01L29/04

CPC classification number: H01L27/0688 ,  H01L21/2007 ,  H01L21/84 ,  H01L27/1203

Abstract: A three dimensional (3D) integrated circuit (IC), 3D IC chip and method of fabricating a 3D IC chip. The chip includes multiple layers of circuits, e.g., silicon insulator (SOI) CMOS IC layers, each including circuit elements. The layers may be formed in parallel and one layer attached to another to form a laminated 3D chip.

Abstract translation: 三维（3D）集成电路（IC），3D IC芯片和3D IC芯片的制造方法。 该芯片包括多层电路，例如硅绝缘体（SOI）CMOS IC层，每层包括电路元件。 这些层可以平行地形成，并且一层附着到另一层以形成层叠的3D芯片。

公开(公告)号：US20060161795A1

公开(公告)日：2006-07-20

申请号：US11375989

申请日：2006-03-14

Applicant: Hans Jacobson ,  Prabhakar Kudva ,  Pradip Bose ,  Peter Cook ,  Stanley Schuster

Inventor： Hans Jacobson ,  Prabhakar Kudva ,  Pradip Bose ,  Peter Cook ,  Stanley Schuster

IPC: G06F1/26

CPC classification number: G06F1/3203 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3275 ,  G06F9/3869 ,  G06F9/3871 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/14

Abstract: An integrated circuit including a pipeline and a method of operating the pipeline. Each stage of the pipeline is triggered by one or more triggering events and are individually, and selectively, stalled by a stall signal. For each stage a stall signal, delayed with respect to the stall signal of a downstream stage, is generated and used to select whether the pipeline stage in question is triggered. A data valid signal propagating with valid data adds further selection, such that only stages with valid data are stalled.

Abstract translation: 一种包括管道的集成电路和操作管道的方法。 流水线的每个阶段由一个或多个触发事件触发，并且由失速信号单独且有选择地停止。 对于每个阶段，产生相对于下游级的失速信号延迟的失速信号，并用于选择是否触发所讨论的流水线级。 用有效数据传播的数据有效信号增加了进一步的选择，使得仅有有效数据的阶段停滞。

公开(公告)号：US20050083081A1

公开(公告)日：2005-04-21

申请号：US10685863

申请日：2003-10-15

Applicant: Hans Jacobson ,  Pradip Bose ,  Alper Buyuktosunoglu ,  Peter Cook ,  Philip Emma ,  Prabhakar Kudva ,  Stanley Schuster

Inventor： Hans Jacobson ,  Pradip Bose ,  Alper Buyuktosunoglu ,  Peter Cook ,  Philip Emma ,  Prabhakar Kudva ,  Stanley Schuster

IPC: H03K5/00 ,  H03K17/16 ,  H03K19/00

CPC classification number: H03K19/0016

Abstract: Leakage current control devices include a circuit having one or more functions in a data path where the functions are executed in a sequence. Each of the functions has power reduction logic to energize each respective function. A leakage control circuit interacts with the power reduction logic, so that the functions are energized or deenergized in a control sequence such that the functions where the data is resident are energized and at least one of the other functions is not energized.

公开(公告)号：US07880194B2

公开(公告)日：2011-02-01

申请号：US12106539

申请日：2008-04-21

Applicant: Matthew J. Breitwisch ,  Chung H. Lam ,  Prabhakar Kudva

Inventor： Matthew J. Breitwisch ,  Chung H. Lam ,  Prabhakar Kudva

IPC: H01L29/66

CPC classification number: H03K19/173

Abstract: A cross-point switch and cross-point switch fabric utilizing phase change material, and method of operating the same. The cross-point switch includes a phase change cross-point circuit containing a plurality of terminal nodes connected to a central node. The connections between the terminal nodes and the central nodes are regulated by phase change switches comprised of a phase change material. The phase change switches being controlled by heating elements capable of melting or crystallizing the phase change material in the phase change switch. The heating elements are operated by a separate heating circuit. Each individual heating element is regulated by an individual transistor.

Abstract translation: 使用相变材料的交叉点开关和交叉点开关织物及其操作方法。 交叉点开关包括包含连接到中央节点的多个终端节点的相变交叉点电路。 终端节点和中心节点之间的连接由相变材料组成的相变开关来调节。 相变开关由能够在相变开关中熔化或结晶相变材料的加热元件控制。 加热元件由单独的加热回路操作。 每个单独的加热元件由单个晶体管调节。

公开(公告)号：US20070294548A1

公开(公告)日：2007-12-20

申请号：US11846847

申请日：2007-08-29

Applicant: Hans JACOBSON ,  Prabhakar Kudva ,  Pradip Bose ,  Peter COOK ,  Stanley SCHUSTER

Inventor： Hans JACOBSON ,  Prabhakar Kudva ,  Pradip Bose ,  Peter COOK ,  Stanley SCHUSTER

IPC: G06F1/26

CPC classification number: G06F1/3203 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3275 ,  G06F9/3869 ,  G06F9/3871 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/14

Abstract: An integrated circuit including a pipeline and a method of operating the pipeline. Each stage of the pipeline is triggered by one or more triggering events and are individually, and selectively, stalled by a stall signal. For each stage a stall signal, delayed with respect to the stall signal of a downstream stage, is generated and used to select whether the pipeline stage in question is triggered. A data valid signal propagating with valid data adds further selection, such that only stages with valid data are stalled.

Abstract translation: 一种包括管道的集成电路和操作管道的方法。 流水线的每个阶段由一个或多个触发事件触发，并且由失速信号单独且有选择地停止。 对于每个阶段，产生相对于下游级的失速信号延迟的失速信号，并用于选择是否触发所讨论的流水线级。 用有效数据传播的数据有效信号增加了进一步的选择，使得仅有有效数据的阶段停滞。