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    Method And Circuit For Testing And Characterizing High Speed Signals Using An ON-Chip Oscilloscope
    12.
    发明申请
    Method And Circuit For Testing And Characterizing High Speed Signals Using An ON-Chip Oscilloscope 审中-公开
    使用片内示波器测试和表征高速信号的方法和电路

    公开(公告)号：US20110234282A1

    公开(公告)日：2011-09-29

    申请号：US13048770

    申请日：2011-03-15

    Applicant: Rajesh Chopra

    Inventor： Rajesh Chopra

    IPC: H03K3/00

    CPC classification number: G01R31/31727 ,  G01R13/0272 ,  G11C29/023 ,  G11C29/028 ,  G11C29/1201 ,  G11C29/48 ,  H03K5/133

    Abstract: A method and structure for characterizing signals used to operate high speed circuitry on an integrated circuit chip. Signals to be characterized, such as column select signals, sense amplifier enable signals and word line signals, are generated on the chip. Each of these signals has an identical corresponding pattern during successive cycles of an input clock signal. These signals are sampled on the chip with successively delayed versions of the input clock signal, thereby generating a plurality of data samples that represent the patterns of the signals over a cycle of the input clock signal. The data samples are stored in a memory block on the chip, and are subsequently serialized and transferred to a location external to the chip.

    Abstract translation: 用于表征用于在集成电路芯片上操作高速电路的信号的方法和结构。 要在芯片上产生要表征的信号，如列选择信号，读出放大器使能信号和字线信号。 这些信号中的每一个在输入时钟信号的连续周期期间具有相同的对应模式。 这些信号在芯片上采用连续延迟版本的输入时钟信号进行采样，从而在输入时钟信号的周期上产生表示信号模式的多个数据样本。 将数据样本存储在芯片上的存储器块中，并随后串行化并传送到芯片外部的位置。

    SYNTHESIZABLE DLL ON SYSTEM-ON-CHIP
    13.
    发明申请
    SYNTHESIZABLE DLL ON SYSTEM-ON-CHIP 有权
    系统在片上的合成DLL

    公开(公告)号：US20110140748A1

    公开(公告)日：2011-06-16

    申请号：US12969220

    申请日：2010-12-15

    Applicant: Prateek Sikka ,  Rajesh Chopra ,  Manoj Yadav

    Inventor： Prateek Sikka ,  Rajesh Chopra ,  Manoj Yadav

    IPC: H03L7/06

    CPC classification number: H03K5/135 ,  G06F17/5045

    Abstract: The present disclosure provides an emulator mapping process on a system-on-a-chip (SoC) for debugging. The implementation reduces manual intervention and makes the emulation mapping process very generic and technology independent and hence it reduces overall project cycle time. In the present disclosure, the SoCs containing analog delay locked loops are made suitable for emulation by configuring analog delay locked loop module in parallel with a synthesizable delay logic module. Further, selection logic is provided to select any one of the module at a time.

    Abstract translation: 本公开提供了用于调试的片上系统（SoC）上的仿真器映射过程。 该实现减少了手动干预，并使仿真映射过程非常通用和独立于技术，从而减少了整个项目周期的时间。 在本公开中，通过与可合成的延迟逻辑模块并联配置模拟延迟锁定环模块，包含模拟延迟锁定环路的SoC适于仿真。 此外，提供选择逻辑以一次选择模块中的任何一个。

    SYSTEM AND METHOD FOR APPLICATION CONFIGURATION COMPARISON AND REUSE
    14.
    发明申请
    SYSTEM AND METHOD FOR APPLICATION CONFIGURATION COMPARISON AND REUSE 失效
    用于应用程序配置比较和重用的系统和方法

    公开(公告)号：US20090228512A1

    公开(公告)日：2009-09-10

    申请号：US12043440

    申请日：2008-03-06

    Applicant: Rajesh Chopra ,  SweeFen Goh ,  Richard Thomas Goodwin ,  Anca-Andreea Ivan ,  Stephen K. Kibby ,  Rakesh Mohan ,  Igor Naumov ,  Thomas Dean Rosinski ,  George A. Shroeder

    Inventor： Rajesh Chopra ,  SweeFen Goh ,  Richard Thomas Goodwin ,  Anca-Andreea Ivan ,  Stephen K. Kibby ,  Rakesh Mohan ,  Igor Naumov ,  Thomas Dean Rosinski ,  George A. Shroeder

    IPC: G06F17/30 ,  G06F3/048

    CPC classification number: G06F8/71 ,  G06Q10/06

    Abstract: A system and method allow a user to extract the set of customizations performed on an application and use these to estimate the time and effort and cost of (a) migrating to a new version of the application and/or (b) consolidating systems. The user can browse the extracted data and select configuration elements for re-use. After downloading the one or more configurations and comparing them, the user selects elements of the configurations for re-use. The first step is to scan one or more application systems and extract the configuration data using a surveyor. The method according to the invention automatically identifies configuration differences. The user then selects configuration elements for re-use. A graphic user interface (GUI) can be provided which allows the user to make these selections by dragging and dropping selected elements to a “To Be” configuration. The selected configurations are then uploaded and installed on an instance of the application.

    Abstract translation: 系统和方法允许用户提取在应用程序上执行的一组定制，并使用它们来估计（a）迁移到新版本的应用程序和/或（b）合并系统的时间和精力和成本。 用户可以浏览提取的数据并选择配置元素以供重复使用。 下载一个或多个配置并对其进行比较后，用户选择配置的元素以供重复使用。 第一步是扫描一个或多个应用系统并使用测量仪提取配置数据。 根据本发明的方法自动识别配置差异。 然后用户选择配置元素以供重用。 可以提供图形用户界面（GUI），其允许用户通过将所选择的元素拖放到“To Be”配置来进行这些选择。 所选配置然后上传并安装在应用程序的实例上。

    Programmable test engine (PCDTE) for emerging memory technologies
    16.
    发明授权
    Programmable test engine (PCDTE) for emerging memory technologies 有权
    用于新兴存储器技术的可编程测试引擎（PCDTE）

    公开(公告)号：US08954803B2

    公开(公告)日：2015-02-10

    申请号：US13030358

    申请日：2011-02-18

    Applicant: Rajesh Chopra

    Inventor： Rajesh Chopra

    IPC: G06F11/00 ,  G06F11/263 ,  G06F11/27 ,  G11C29/56

    CPC classification number: G06F11/263 ,  G06F11/27 ,  G11C29/56 ,  G11C29/56004

    Abstract: A programmable characterization-debug-test engine (PCDTE) on an integrated circuit chip. The PCDTE includes an instruction memory that receives and stores instructions provided on a chip interface, and a configuration memory that receives and stores configuration values provided on the chip interface. The PCDTE also includes a controller that configures a plurality of address counters and data registers in response to the configuration values. The controller also executes the instructions, wherein read/write addresses and write data are retrieved from the counters in response to the instructions. The retrieved read/write addresses and write data are used to access a memory under test. Multiple ports of the memory under test may be simultaneously accessed. Multiple instructions may be linked. The instructions may specify special counting functions within the counters and/or specify integrated (linked) counters. The PCDTE may transmit information off of the chip to exercise transmit/receive circuitry of the chip.

    Abstract translation: 集成电路芯片上的可编程特征调试测试引擎（PCDTE）。 PCDTE包括接收并存储提供在芯片接口上的指令的指令存储器，以及接收并存储在芯片接口上提供的配置值的配置存储器。 PCDTE还包括响应于配置值配置多个地址计数器和数据寄存器的控制器。 控制器还执行指令，其中响应于指令从计数器检索读/写地址和写数据。 检索到的读/写地址和写数据用于访问被测内存。 可以同时访问被测存储器的多个端口。 可以链接多个指令。 指令可以指定计数器内的特殊计数功能和/或指定集成（链接）计数器。 PCDTE可以从芯片传送信息来锻炼芯片的发射/接收电路。

    System and method of integrated circuit testing
    18.
    发明授权
    System and method of integrated circuit testing 失效
    集成电路测试的系统和方法

    公开(公告)号：US07587643B1

    公开(公告)日：2009-09-08

    申请号：US11213043

    申请日：2005-08-25

    Applicant: Rajesh Chopra

    Inventor： Rajesh Chopra

    IPC: G01R31/28

    CPC classification number: G01R31/318544 ,  G01R31/318555 ,  G01R31/318558

    Abstract: An integrated circuit may include a packet decoder to receive serial data and to decode JTAG signals from the packets received. A JTAG processor may test the electrical circuitry dependent on the JTAG signals decoded. In a further embodiment, a test system may include a library of selectable JTAG routines. An encoder may encode a signal with serial data representative of sequential JTAG signals for at least one of the selectable JTAG routines. In a method of testing, the integrated circuit may receive the serial data signal at a predetermined terminal. A portion of the serial data may be examined to determine the presence of a predefined signature key. JTAG data may then be parsed from the serial data and tests performed based on the parsed JTAG data.

    Abstract translation: 集成电路可以包括用于接收串行数据并从所接收的分组中解码JTAG信号的分组解码器。 JTAG处理器可以根据解码的JTAG信号测试电路。 在另一个实施例中，测试系统可以包括可选择的JTAG例程库。 编码器可以编码具有表示用于可选择的JTAG例程中的至少一个的顺序JTAG信号的串行数据的信号。 在一种测试方法中，集成电路可以在预定的终端处接收串行数据信号。 可以检查一部分串行数据以确定预定义签名密钥的存在。 然后可以从串行数据中分析JTAG数据，并根据解析的JTAG数据执行测试。

    Microprocessor having improved memory management unit and cache memory
    19.
    发明授权
    Microprocessor having improved memory management unit and cache memory 失效

    公开(公告)号：US06598128B1

    公开(公告)日：2003-07-22

    申请号：US09410567

    申请日：1999-10-01

    Applicant: Shinich Yoshioka ,  David Shepherd ,  Rajesh Chopra

    Inventor： Shinich Yoshioka ,  David Shepherd ,  Rajesh Chopra

    IPC: G06F1200

    CPC classification number: G06F12/1063 ,  G06F12/0835

    Abstract: Methods of maintaining cache coherency of a virtual cache memory system in a data processing system are disclosed. The entries of the virtual cache memory include physical address information and logical address information. A memory access operation may be initiated on one or more predetermined memory locations based on physical address information. A determination may be made if the memory access operation may involve cache coherent memory. If the memory access operation may involve cache coherent memory, then a cache coherency command may be issued that contains physical address information of the memory access operation. Based on the cache coherency command and the physical address information, a determination may be made if there is a match between the physical address information of the memory access operation and the physical address information stored in the virtual cache. If there is a match, then a determination may be made whether data associated with the particular entry of the virtual cache memory is dirty. If the data associated with the particular entry of the virtual cache memory is dirty, then a write back operation may be initiated, and data in the particular entry of the virtual cache memory may be written to memory. A command may then be issued that indicates that the virtual cache memory and the memory locations of the memory access operation are cohered, and the memory access operation may be completed. A determination also may be made whether the memory access operation is a write operation. If the memory access operation is a write operation, then the particular entry of the virtual cache memory may be invalidated. The virtual cache memory may be included in a single chip microprocessor, and a device external to the single chip microprocessor may initiate the memory access operation. A circuit that bridges between the external device and an internal bus may receive a command from the external device to initiate the memory access operation.

    Microprocessor having improved memory management unit and cache memory
    20.
    发明授权
    Microprocessor having improved memory management unit and cache memory 有权
    具有改进的存储器管理单元和高速缓冲存储器的微处理器

    公开(公告)号：US06553460B1

    公开(公告)日：2003-04-22

    申请号：US09410505

    申请日：1999-10-01

    Applicant: Rajesh Chopra ,  Shinichi Yoshioka ,  Mark Debbage

    Inventor： Rajesh Chopra ,  Shinichi Yoshioka ,  Mark Debbage

    IPC: G06F1200

    CPC classification number: G06F9/30047 ,  G06F9/30087 ,  G06F9/3836 ,  G06F9/3855 ,  G06F9/3857 ,  G06F12/0808 ,  G06F12/0831 ,  G06F12/1063

    Abstract: Methods of managing a cache memory system in a data processing system are disclosed. The data processing system executes instructions and stores and receives data from a memory having locations in a memory space. The entries of the cache memory are in locations in a register space separate from the memory space. A first instruction that operates only on locations in a register space but not on locations in memory space may be executed to obtain address information from at least one entry of the cache memory. The obtained address information be compared with target address information. If the comparison between the obtained address information and the target address information results in a correspondence, then a first operation may be performed on the entry of the cache memory. If the comparison between the obtained address information and the target address information does not result in a correspondence, then the fit first operations not performed on the entry of the cache memory. Management operations may thus be performed on the cache memory without using locations in memory space. The first operation may include invalidate, flush or purge operations. The cache memory may be a virtual cache memory that has a plurality of entries each including physical address information and logical address information. The obtained address information, may be logical address information or physical address information. The first instruction may be a GET instruction for reading information from entries of the translation lookaside buffer or the cache memory. The second instruction may be a PUT instruction for writing information to entries of the translation lookaside buffer or the cache memory.

    Abstract translation: 公开了一种在数据处理系统中管理高速缓冲存储器系统的方法。 数据处理系统执行指令并存储并从存储器空间中具有位置的存储器接收数据。 高速缓冲存储器的条目位于与存储器空间分开的寄存器空间中的位置。 可以执行仅在寄存器空间中的位置而不在存储器空间中的位置上操作的第一指令，以从高速缓冲存储器的至少一个条目获得地址信息。 将获得的地址信息与目标地址信息进行比较。 如果获得的地址信息和目标地址信息之间的比较导致对应关系，则可以对高速缓冲存储器的条目执行第一操作。 如果所获得的地址信息与目标地址信息之间的比较不产生对应关系，则对高速缓冲存储器的条目不进行适合的第一操作。 因此，可以在高速缓冲存储器上执行管理操作，而不使用存储空间中的位置。 第一个操作可能包括无效，冲洗或清除操作。 高速缓冲存储器可以是具有多个条目的虚拟高速缓冲存储器，每个条目包括物理地址信息和逻辑地址信息。 所获得的地址信息可以是逻辑地址信息或物理地址信息。 第一指令可以是用于从翻译后备缓冲器或高速缓冲存储器的条目读取信息的GET指令。 第二指令可以是用于将信息写入到翻译后备缓冲器或高速缓冲存储器的条目的PUT指令。

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