公开(公告)号：US20250053191A1

公开(公告)日：2025-02-13

申请号：US18795290

申请日：2024-08-06

Applicant: Renesas Electronics Corporation

Inventor： Yoichi MAEDA ,  Jun MATSUSHIMA

IPC: G06F1/12

Abstract: The technology provided enables the acceleration of the clock. The semiconductor device comprises a counter circuit configured to generate a read signal when the count number reaches a predetermined number, a buffer configured to store test data and sequentially output the test data in the order stored when the read signal indicates a valid value, and a first scan test circuit that sequentially captures the test data output from the buffer.

公开(公告)号：US20250040222A1

公开(公告)日：2025-01-30

申请号：US18772473

申请日：2024-07-15

Applicant: Renesas Electronics Corporation

Inventor： Yu NAGAHAMA

IPC: H01L29/40 ,  H01L21/28 ,  H01L21/311 ,  H01L29/423

Abstract: The reliability of the semiconductor device is improved. A field plate electrode FP is formed inside the trench TR via an insulating film IF1. The other part of the field plate electrode FP is selectively retracted toward the bottom of the trench TR so that a part of the field plate electrode FP remains as a lead-out part FPa. A silicon oxide film OX1 is formed on the upper surface of the field plate electrode FP by thermal oxidation. The insulating film IF1 located on the upper surface TS of the semiconductor substrate SUB and the silicon oxide film OX1 are removed, and the insulating film IF1 is retracted so that its upper surface position is lower than the upper surface position of the field plate electrode FP.

公开(公告)号：US20250037744A1

公开(公告)日：2025-01-30

申请号：US18777820

申请日：2024-07-19

Applicant: Renesas Electronics Corporation

Inventor： Toshiki KIRYU ,  Toma OGATA ,  Kosuke YAYAMA ,  Toyohiro SHIMOGAWA

IPC: G11C5/14 ,  G11C7/22 ,  H02M3/158

Abstract: While suppressing the influence of voltage noise, the adjustment range of the power supply voltage generated based on the reference voltage is expanded. The semiconductor device includes a reference voltage generation circuit, a regulator, a buffer, and a voltage control circuit. The reference voltage generation circuit is configured to be able to adjust the reference voltage. The regulator is configured to be able to change the output ratio of the power supply voltage to the reference voltage based on the control signal. The semiconductor device further includes a voltage control circuit for outputting a voltage control signal to the regulator to switch the output ratio.

公开(公告)号：US12212639B2

公开(公告)日：2025-01-28

申请号：US18384574

申请日：2023-10-27

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Christian Mardmoeller ,  Dnyaneshwar Kulkarni ,  Thorsten Hoffleit

IPC: H04L69/08 ,  H04L12/66 ,  H04L45/741 ,  H04L69/18 ,  H04L45/302 ,  H04L69/325

Abstract: A message handler is described. The message handler is configured, in response to receiving a data package which is formatted according to a given communications protocol, such as CAN or Ethernet, and which comprises package-directing data and payload data, to generate package having a predetermined data format, for example a layer-2 or layer-3 package, which comprises a header and payload data. The header comprises an address generated in dependence upon the package-directing data and wherein the payload comprises the data package. The package having a predetermined data format may be an IEEE 1722 frame.

公开(公告)号：US20250022794A1

公开(公告)日：2025-01-16

申请号：US18768246

申请日：2024-07-10

Applicant: Renesas Electronics Corporation

Inventor： Takayuki IGARASHI ,  Yasutaka NAKASHIBA

IPC: H01L23/522 ,  H01L27/02

Abstract: A semiconductor device includes a semiconductor substrate, a first coil, a second coil, a third coil, and a fourth coil, an insulating layer, and a first shield. The semiconductor substrate has a device region and a peripheral region. The peripheral region is present around the device region in a plan view. The first coil and the second coil are arranged on the device region and are arranged in a first direction in a plan view. The third coil and the fourth coil are respectively opposed to the first coil and the second coil via the insulating layer. The first shield is arranged between the semiconductor substrate and the first and second coils and overlaps with the first coil and the second coil in a plan view. A width of the first shield in a second direction orthogonal to the first direction is larger than a width of the first coil in the second direction and a width of the second coil in the second direction. The first shield is electrically connected to a reference potential.

公开(公告)号：US20250015200A1

公开(公告)日：2025-01-09

申请号：US18666131

申请日：2024-05-16

Applicant: Renesas Electronics Corporation

Inventor： Keiichi FURUYA

IPC: H01L29/866 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/08 ,  H01L29/66

Abstract: A semiconductor substrate includes a p-type substrate body, an n-type buried layer on the p-type substrate body, and a p-type semiconductor layer on the n-type buried layer. A DTI region penetrates through the p-type semiconductor layer and the n-type buried layer, and reaches the p-type substrate body. An n-type semiconductor region, which is a cathode region of a Zener diode, and a p-type anode region of the Zener diode are formed in the semiconductor layer. The p-type anode region includes a p-type first semiconductor region formed under the n-type semiconductor region, and a p-type second semiconductor region formed under the p-type first semiconductor region. A PN junction is formed between the p-type first semiconductor region and the n-type semiconductor region. An impurity concentration of the p-type second semiconductor region is higher than an impurity concentration of the p-type first semiconductor region.

公开(公告)号：US20250015146A1

公开(公告)日：2025-01-09

申请号：US18763910

申请日：2024-07-03

Applicant: Renesas Electronics Corporation

Inventor： Yotaro GOTO

IPC: H01L29/40 ,  H01L29/66 ,  H01L29/78

Abstract: A dielectric film, which contacts a field plate electrode, is formed between the field plate electrode and a gate electrode, and a recess is formed at an upper surface of the dielectric film and between a drain region and the gate electrode.

公开(公告)号：US12182045B2

公开(公告)日：2024-12-31

申请号：US18152582

申请日：2023-01-10

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kazuaki Terashima ,  Atsushi Nakamura ,  Rajesh Ghimire

IPC: G06F13/28 ,  G06F7/544 ,  G06F13/16

Abstract: A semiconductor device capable of preventing a sharp variation in current consumption in neural network processing is provided. A dummy circuit outputs dummy data to at least one or more of n number of MAC circuits and causes the at least one or more of n number of MAC circuits to perform a dummy calculation and to output dummy output data. An output-side DMA controller transfers pieces of normal output data from the n number of MAC circuits to a memory, by use of n number of channels, respectively, and does not transfer the dummy output data to the memory. In this semiconductor device, the at least one or more of n number of MAC circuits perform the dummy calculation in a period from a timing at which the output-side DMA controller ends data transfer to the memory to a timing at which the input-side DMA controller starts data transfer from the memory.

公开(公告)号：US20240429159A1

公开(公告)日：2024-12-26

申请号：US18666149

申请日：2024-05-16

Applicant: Renesas Electronics Corporation

Inventor： Yasutaka NAKASHIBA ,  Takayuki IGARASHI

IPC: H01L23/522 ,  H01L23/528 ,  H01L27/01

Abstract: Providing a semiconductor device that can suppress the heat generation in a transformer. The semiconductor device comprises first, second, third and fourth coils, a lead wire, and an insulating layer. The lead wire is formed on the same layer as the first and second coils. The first and second coils are adjacent to each other through the lead wire in a plan view and are electrically connected in series through the lead wire. The insulating layer covers the first and second coils, and the lead wire. The third coil is formed on the first coil so as to face the first coil through the insulating layer. The fourth coil is formed on the second coil so as to face the second coil through the insulating layer. The third and fourth coils are adjacent to each other in a plan view and are electrically connected to each other.

公开(公告)号：US12174691B2

公开(公告)日：2024-12-24

申请号：US18061776

申请日：2022-12-05

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takuro Nishikawa

IPC: G06F11/00 ,  G06F11/07

Abstract: The semiconductor device 10 receives an input signal given from the signal generating unit provided externally by a plurality of receiving units, a receiving unit 12, 13 for generating a plurality of received signals from the received input signal, a plurality of received signals by comparing, an error determination unit 14 for outputting an error notification to the upper system in response to the error between the channels that occurs between the received signals becomes equal to or greater than the threshold value, the threshold count value is stored and a threshold count register 17, the error determination unit 14 waits for the departure of the error notification until the period specified by the threshold count value has elapsed.