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公开(公告)号：US12135642B2
公开(公告)日：2024-11-05
申请号：US18186476
申请日：2023-03-20
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Kazuaki Terashima , Atsushi Nakamura , Yonghua Wang
Abstract: A semiconductor device capable of reducing power consumption is provided. A group controller detects a zero weight parameter having a zero value among “n×m” weight parameters to be transferred to a weight parameter buffer. Then, when receiving the zero weight parameter as its input, the group controller exchanges the “n×m” weight parameters to be transferred to the weight parameter buffer so that all multiplication results of the “n” multipliers included in a target multiplier group that is one of the “m” multiplier groups are zero. The group controller controls the target multiplier group to be disabled, and exchanges the “n×m” pixel data to be transferred to the data input buffer, based on the exchange of the “n×m” weight parameters.
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公开(公告)号：US11455248B2
公开(公告)日：2022-09-27
申请号：US16868041
申请日：2020-05-06
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Atsushi Nakamura , Akihiro Yamamoto , Kazuaki Terashima , Manabu Koike
Abstract: A semiconductor device performs a software lock-step. The semiconductor device includes a first circuit group including a first Intellectual Property (IP) to be operated in a first address space, a first bus, and a first memory, a second circuit group including a second IP to be operated in a second address space, a second bus, and a second memory, a third bus connectable to a third memory, and a transfer control circuit coupled to the first to third buses. when the software lock-step is performed, the second circuit group converts an access address from the second IP to the second memory such that an address assigned to the second memory in the second address space is a same as an address assigned to the first memory in the first address space.
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公开(公告)号：US09503637B2
公开(公告)日：2016-11-22
申请号：US14530770
申请日：2014-11-02
Applicant: Renesas Electronics Corporation
Inventor： Hiroyuki Hamasaki , Atsushi Nakamura , Manabu Koike , Hideaki Kido , Nobuyasu Kanekawa
CPC classification number: H04N5/77 , G06T1/20 , G06T1/60 , G06T2200/28 , H04N5/23229 , H04N5/265 , H04N5/91
Abstract: An image processing apparatus includes an image processing unit that calculates two types of image data from one image data and outputs the calculated image data, a data combination unit that combines the two type of data supplied from the image processing unit and outputs the combined data to one terminal, an output buffer that adjusts an output timing of the combined data according to an instruction supplied from bus arbitration means for arbitrating a bus, and a data distribution unit that outputs the combined data output from the output buffer to the bus in a form of the combined data, or distributes the combined data and outputs the distributed data to the bus according to an external combination distribution instruction.
Abstract translation: 图像处理装置包括图像处理单元，其从一个图像数据计算两种图像数据并输出计算出的图像数据;数据组合单元，其组合从图像处理单元提供的两种数据，并将该组合数据输出到 一个终端，输出缓冲器，根据从用于仲裁总线的总线仲裁装置提供的指令调整组合数据的输出定时;以及数据分配单元，其以从形式输出从输出缓冲器输出到总线的组合数据 或者分发组合数据，并根据外部组合分配指令将分布式数据输出到总线。
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公开(公告)号：US12182045B2
公开(公告)日：2024-12-31
申请号：US18152582
申请日：2023-01-10
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Kazuaki Terashima , Atsushi Nakamura , Rajesh Ghimire
Abstract: A semiconductor device capable of preventing a sharp variation in current consumption in neural network processing is provided. A dummy circuit outputs dummy data to at least one or more of n number of MAC circuits and causes the at least one or more of n number of MAC circuits to perform a dummy calculation and to output dummy output data. An output-side DMA controller transfers pieces of normal output data from the n number of MAC circuits to a memory, by use of n number of channels, respectively, and does not transfer the dummy output data to the memory. In this semiconductor device, the at least one or more of n number of MAC circuits perform the dummy calculation in a period from a timing at which the output-side DMA controller ends data transfer to the memory to a timing at which the input-side DMA controller starts data transfer from the memory.
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公开(公告)号：US09978117B2
公开(公告)日：2018-05-22
申请号：US14164211
申请日：2014-01-26
Applicant: Renesas Electronics Corporation
Inventor： Manabu Koike , Akihiro Yamamoto , Atsushi Nakamura , Hideaki Kido
IPC: G06T1/60
CPC classification number: G06T1/60
Abstract: A semiconductor apparatus pertaining to one embodiment has: a first processor that operates by a first program and reads pixel data from a storage unit; a second processor that operates by a second program, performs processing to the pixel data, and writes the processed pixel data back to the storage unit; and a buffer circuit that transfers the pixel data from the first processor to the second processor.
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Patent Agency Ranking
公开(公告)号：US20140193954A1
公开(公告)日：2014-07-10
申请号：US14204988
申请日：2014-03-11
Applicant: Renesas Electronics Corporation
Inventor： Naoto Taoka , Atsushi Nakamura , Naozumi Morino , Toshikazu Ishikawa , Nobuhiro Kinoshita
IPC: H01L23/00
CPC classification number: H01L24/81 , H01L21/563 , H01L23/3128 , H01L23/5226 , H01L23/5283 , H01L23/5286 , H01L24/05 , H01L24/06 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/97 , H01L25/0657 , H01L25/18 , H01L2224/02166 , H01L2224/0401 , H01L2224/04042 , H01L2224/05093 , H01L2224/05553 , H01L2224/05599 , H01L2224/06515 , H01L2224/1134 , H01L2224/13144 , H01L2224/14515 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/48599 , H01L2224/49171 , H01L2224/49175 , H01L2224/4943 , H01L2224/73203 , H01L2224/73204 , H01L2224/73265 , H01L2224/81193 , H01L2224/81203 , H01L2224/81801 , H01L2224/83102 , H01L2224/92125 , H01L2224/97 , H01L2225/0651 , H01L2225/06517 , H01L2225/06562 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01083 , H01L2924/014 , H01L2924/14 , H01L2924/15184 , H01L2924/15311 , H01L2924/181 , H01L2924/30107 , H01L2924/3011 , H01L2224/85 , H01L2224/83 , H01L2224/81 , H01L2924/00012 , H01L2924/00 , H01L2224/92247
Abstract: The reliability of a semiconductor device is to be improved. A microcomputer chip (semiconductor chip) having a plurality of pads formed on a main surface thereof is mounted over an upper surface of a wiring substrate in an opposed state of the chip main surface to the substrate upper surface. Pads coupled to a plurality of terminals (bonding leads) formed over the substrate upper surface comprise a plurality of first pads in which a unique electric current different from the electric current flowing through other pads flows and a plurality of second pads in which an electric current common to the pads flows or does not flow. Another first pad of the first pads or one of the second pads are arranged next to the first pad. The first pads are electrically coupled to a plurality of bonding leads respectively via a plurality of bumps (first conductive members), while the second pads are bonded to the terminals via a plurality of bumps (second conductive members).
Abstract translation: 要提高半导体器件的可靠性。 具有形成在其主表面上的多个焊盘的微计算机芯片（半导体芯片）以与芯片主表面相对的状态安装在布线基板的上表面上。 耦合到形成在衬底上表面上的多个端子（接合引线）的焊盘包括多个第一焊盘，其中与流过其它焊盘的电流不同的独特电流流过多个第二焊盘，其中电流 焊盘共同流动或不流动。 第一焊盘或第二焊盘中的一个的另一个第一焊盘布置在第一焊盘的旁边。 第一焊盘分别经由多个凸起（第一导电构件）电耦合到多个接合引线，而第二焊盘通过多个凸块（第二导电构件）接合到端子。
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公开(公告)号：US09986196B2
公开(公告)日：2018-05-29
申请号：US15290831
申请日：2016-10-11
Applicant: Renesas Electronics Corporation
Inventor： Hiroyuki Hamasaki , Atsushi Nakamura , Manabu Koike , Hideaki Kido , Nobuyasu Kanekawa
CPC classification number: H04N5/77 , G06T1/20 , G06T1/60 , G06T2200/28 , H04N5/23229 , H04N5/265 , H04N5/91
Abstract: An image processing apparatus includes an image processing unit that calculates two types of image data from one image data and outputs the calculated image data, a data combination unit that combines the two type of data supplied from the image processing unit and outputs the combined data to one terminal, an output buffer that adjusts an output timing of the combined data according to an instruction supplied from bus arbitration means for arbitrating a bus, and a data distribution unit that outputs the combined data output from the output buffer to the bus in a form of the combined data, or distributes the combined data and outputs the distributed data to the bus according to an external combination distribution instruction.
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8.发明授权公开(公告)号：US11763417B2
公开(公告)日：2023-09-19
申请号：US17531302
申请日：2021-11-19
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Kazuaki Terashima , Isao Nagayoshi , Atsushi Nakamura
CPC classification number: G06T1/20 , G06T1/0007 , G06T3/4015 , G06T7/11
Abstract: The semiconductor device includes an image signal processor, a scaler, and an ROI (Region of Interest) controller. The image signal processor executes image processing including demosaic processing and stores the image after the image processing in memory. The scaler reduces the capture image from the image sensor to generate a reduced entire image and causes the image signal processor to execute image processing on the reduced entire image. The ROI controller cuts out a partial region of the captured image from the image sensor to generate an ROI image and causes the image signal processor to execute image processing on the ROI image.
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公开(公告)号：US10511799B2
公开(公告)日：2019-12-17
申请号：US16133351
申请日：2018-09-17
Applicant: Renesas Electronics Corporation
Inventor： Hiroyuki Hamasaki , Atsushi Nakamura , Manabu Koike , Hideaki Kido , Nobuyasu Kanekawa
Abstract: An image processing apparatus includes an image processing unit that calculates two types of image data from one image data and outputs the calculated image data, a data combination unit that combines the two type of data supplied from the image processing unit and outputs the combined data to one terminal, an output buffer that adjusts an output timing of the combined data according to an instruction supplied from bus arbitration means for arbitrating a bus, and a data distribution unit that outputs the combined data output from the output buffer to the bus in a form of the combined data, or distributes the combined data and outputs the distributed data to the bus according to an external combination distribution instruction.
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公开(公告)号：US10108476B2
公开(公告)日：2018-10-23
申请号：US14825739
申请日：2015-08-13
Applicant: Renesas Electronics Corporation
Inventor： Motoyasu Takabatake , Akihiro Yamamoto , Atsushi Nakamura
Abstract: The execution time of a self diagnosis program is reduced. A compiler apparatus includes: a specify unit that specifies, out of a plurality of resources included in a diagnosis target apparatus, a use resource group being a set of resources used by an instruction string included in an object program executed on the diagnosis target apparatus; a determine unit that determines, in accordance with the specified use resource group, a target resource group being a set of resources to be targets of a self diagnosis in the diagnosis target apparatus; and an output unit that outputs, for causing the self diagnosis on the determined target resource group to be executed in the diagnosis target apparatus, information based on the target resource group to the diagnosis target apparatus.
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