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19 条记录 (耗时 0.016 秒)

    Multi-bit digital input using a single pin
    11.
    发明授权
    Multi-bit digital input using a single pin 有权
    使用单个引脚的多位数字输入

    公开(公告)号：US06967591B1

    公开(公告)日：2005-11-22

    申请号：US10124658

    申请日：2002-04-15

    申请人： David M. Dwelley ,  Robert L. Reay

    发明人： David M. Dwelley ,  Robert L. Reay

    IPC分类号： H03K19/173 ,  H03M5/20 ,  H04L25/49 ,  G08C19/16

    CPC分类号： H03K19/1732 ,  H04L25/49

    摘要： Electronic devices, and methods, for transmitting, transferring and/or conveying a multi-bit digital signal as a voltage signal via a single pin. Devices and methods according to the invention substantially reduce the pin count of a device because inputting of a multi-bit digital signal preferably does not use more than one input pin. In addition, the speed of transmission is improved because the multi-bit digital signal is transmitted as a voltage signal substantially at one time as opposed to serially.

    摘要翻译： 用于通过单个引脚传输，传送和/或传送多位数字信号作为电压信号的电子设备和方法。 根据本发明的装置和方法基本上减少了装置的引脚数，因为多位数字信号的输入优选地不使用多于一个的输入引脚。 此外，与串行相反，多位数字信号基本上一次作为电压信号发送，从而提高了传输速度。

    Constant-current/constant-voltage circuit architecture
    12.
    发明授权
    Constant-current/constant-voltage circuit architecture 有权

    公开(公告)号：US06819094B2

    公开(公告)日：2004-11-16

    申请号：US10716129

    申请日：2003-11-17

    申请人： Trevor W. Barcelo ,  Robert L. Reay ,  David M. Dwelley

    发明人： Trevor W. Barcelo ,  Robert L. Reay ,  David M. Dwelley

    IPC分类号： G05F316

    CPC分类号： H02M3/158 ,  G05F3/262

    摘要： Methods and circuits implementing a constant-current/constant-voltage circuit architecture are provided. The methods and circuits preferably provide a charging system that provides current to a load using a fixed current until the load is charged. When the load is charged, the methods and circuits preferably provide a variable current to the load in order to maintain the voltage level across the load. This variable current varies according to the voltage across the load. In one embodiment of the invention, a constant power current may also be used as one of the load charging currents. The constant power current may act as a limit on the charging circuit's power output.

    Constant-current/constant-voltage current supply
    13.
    发明授权
    Constant-current/constant-voltage current supply 有权

    公开(公告)号：US06570372B2

    公开(公告)日：2003-05-27

    申请号：US10106499

    申请日：2002-03-27

    申请人： Trevor W. Barcelo ,  Robert L. Reay ,  David M. Dwelley

    发明人： Trevor W. Barcelo ,  Robert L. Reay ,  David M. Dwelley

    IPC分类号： G05F316

    CPC分类号： H02M3/158 ,  G05F3/262

    摘要： Methods and circuits implementing a constant-current/constant-voltage circuit architecture are provided. The methods and circuits preferably provide a charging system that provides current to a load using a fixed current until the load is charged. When the load is charged, the methods and circuits preferably provide a variable current to the load in order to maintain the voltage level across the load. This variable current varies according to the voltage across the load. In one embodiment of the invention, a constant power current may also be used as one of the load charging currents. The constant power current may act as a limit on the charging circuit's power output.

    Schottky enhanced CMOS output circuit
    15.
    发明授权
    Schottky enhanced CMOS output circuit 失效
    肖特基增强CMOS输出电路

    公开(公告)号：US5015889A

    公开(公告)日：1991-05-14

    申请号：US314378

    申请日：1989-02-23

    申请人： Robert L. Reay

    发明人： Robert L. Reay

    IPC分类号： H01L27/06 ,  H01L27/092 ,  H03K19/003 ,  H03K19/094 ,  H03K19/0948

    CPC分类号： H01L27/0629 ,  H01L27/092 ,  H03K19/00315 ,  H03K19/09429 ,  H03K19/0948

    摘要： The high impedance state of a tri-state CMOS transistor output circuit is enhanced by serially connecting first and second Schottky diodes with the P-channel transistor and the N-channel transistor whereby in the high impedance state reverse bias of the substrate/source-drain diodes of the two transistors is prevented when the output of the circuit is taken beyond the supply voltage potentials of the output circuit.

    摘要翻译： 通过将第一和第二肖特基二极管与P沟道晶体管和N沟道晶体管串联连接，增强了三态CMOS晶体管输出电路的高阻抗状态，由此在衬底/源极 - 漏极 当电路的输出超出输出电路的电源电压时，防止两个晶体管的二极管。

    MONOLITHIC VOLTAGE REFERENCE DEVICE WITH INTERNAL, MULTI-TEMPERATURE DRIFT DATA AND RELATED TESTING PROCEDURES
    16.
    发明申请
    MONOLITHIC VOLTAGE REFERENCE DEVICE WITH INTERNAL, MULTI-TEMPERATURE DRIFT DATA AND RELATED TESTING PROCEDURES 有权
    具有内部，多温度数据和相关测试程序的单片电压参考设备

    公开(公告)号：US20100301923A1

    公开(公告)日：2010-12-02

    申请号：US12475184

    申请日：2009-05-29

    申请人： Michael B. Anderson ,  Tahir M. Hasoon ,  Brendan J. Whelan ,  J. Spencer Wright ,  Robert L. Reay

    发明人： Michael B. Anderson ,  Tahir M. Hasoon ,  Brendan J. Whelan ,  J. Spencer Wright ,  Robert L. Reay

    IPC分类号： G01R19/00 ,  H01L35/00

    CPC分类号： G01R31/2849 ,  G01R31/2874 ,  G01R35/007

    摘要： A testing procedure may determine whether a monolithic voltage reference device meets a temperature drift specification. A first non-room temperature output voltage of the monolithic voltage reference device may be measured while the monolithic voltage reference device is at a first non-room temperature which is substantially different than room temperature. First non-room temperature information may be stored in a memory within the monolithic voltage reference device which is a function of the first non-room temperature output voltage. A second non-room temperature output voltage of the monolithic voltage reference device may be measured while the monolithic voltage reference device is at a second non-room temperature which is substantially different than the room temperature and the first non-room temperature. Second non-room temperature information may be stored in the memory without destroying the first non-room temperature information which is a function of the second non-room temperature output voltage. A determination may be made whether the monolithic voltage reference device meets the temperature drift specification based on a computation that is a function of both the first non-room temperature information and the second non-room temperature information.

    摘要翻译： 测试程序可以确定单片电压参考装置是否满足温度漂移规范。 单片电压参考装置的第一非室温输出电压可以被测量，而单片电压参考装置处于与室温基本不同的第一非室温。 第一非室温信息可以存储在作为第一非室温输出电压的函数的单片电压参考装置内的存储器中。 单片电压参考装置的第二非室温输出电压可以被测量，而单片电压参考装置处于与室温和第一非室温基本上不同的第二非室温。 可以将第二非室温信息存储在存储器中，而不破坏作为第二非室温输出电压的函数的第一非室温信息。 可以基于作为第一非室内温度信息和第二非室内温度信息的函数的计算来确定单片电压参考装置是否满足温度漂移规格。

    Constant-current/constant-voltage current supply
    17.
    发明授权
    Constant-current/constant-voltage current supply 有权
    恒流/恒压电源

    公开(公告)号：US06522118B1

    公开(公告)日：2003-02-18

    申请号：US09837658

    申请日：2001-04-18

    申请人： Trevor W. Barcelo ,  Robert L. Reay ,  David M. Dwelley

    发明人： Trevor W. Barcelo ,  Robert L. Reay ,  David M. Dwelley

    IPC分类号： G05F316

    CPC分类号： H02M3/158 ,  G05F3/262

    摘要： Methods and circuits implementing a constant-current/constant-voltage circuit architecture are provided. The methods and circuits preferably provide a charging system that provides current to a load using a fixed current until the load is charged. When the load is charged, the methods and circuits preferably provide a variable current to the load in order to maintain the voltage level across the load. This variable current varies according to the voltage across the load. In one embodiment of the invention, a constant power current may also be used as one of the load charging currents. The constant power current may act as a limit on the charging circuit's power output.

    摘要翻译： 提供实现恒流/恒压电路架构的方法和电路。 方法和电路优选地提供一种充电系统，其使用固定电流向负载提供电流，直到负载被充电。 当负载充电时，方法和电路优选地向负载提供可变电流，以便跨过负载保持电压电平。 该可变电流根据负载上的电压而变化。 在本发明的一个实施例中，恒定功率电流也可以用作负载充电电流之一。 恒定功率电流可充当充电电路的功率输出限制。

    Analog-to-digital converter
    18.
    发明授权
    Analog-to-digital converter 失效
    模数转换器

    公开(公告)号：US5714955A

    公开(公告)日：1998-02-03

    申请号：US486862

    申请日：1995-06-07

    申请人： Robert L. Reay ,  Yang-Long Teo ,  William C. Rempfer

    发明人： Robert L. Reay ,  Yang-Long Teo ,  William C. Rempfer

    IPC分类号： H03M1/00 ,  H03M1/12

    CPC分类号： H03M1/002 ,  H03M1/12

    摘要： Serial analog-to-digital converters (ADC) in which power down and power up modes are activated by two dual-purpose input signals are provided. The ADCs of the invention eliminate the need for a dedicated power down input line as found on typical serial ADCs. When commanded to do so, the ADC enters into one of two power down modes, NAP or SLEEP. In NAP mode, only those portions of the ADC circuit which consume current and which are capable of waking up almost instantaneously are powered down. In SLEEP mode, the entire ADC circuit is powered down. When commanded to do so, the ADC enters into a power up mode, applying current to every portion of the ADC circuit. Wake-up from the NAP mode takes place almost instantaneously. Wake-up from the SLEEP mode requires additional time. From either mode, a signal is generated when the ADC conversion circuit, which preferably includes a reference voltage generator, has stabilized sufficiently for the ADC to perform analog-to-digital conversion.

    摘要翻译： 提供了通过两个双用途输入信号激活掉电和上电模式的串行模数转换器（ADC）。 本发明的ADC消除了对典型串行ADC所发现的专用掉电输入线的需要。 当指令这样做时，ADC进入两种掉电模式之一NAP或SLEEP。 在NAP模式下，只有那些消耗电流且几乎瞬间唤醒的ADC电路的那些部分掉电。 在休眠模式下，整个ADC电路掉电。 当指令这样做时，ADC进入上电模式，将电流施加到ADC电路的每个部分。 从NAP模式唤醒几乎瞬间发生。 从休眠模式唤醒需要额外的时间。 在任一模式下，当ADC转换电路（其优选地包括参考电压发生器）已经足够稳定以使ADC执行模数转换时产生信号。