公开(公告)号：US11824681B2

公开(公告)日：2023-11-21

申请号：US17814113

申请日：2022-07-21

Applicant: STMicroelectronics Design & Application S.R.O. ,  STMicroelectronics Application GMBH

Inventor： Vaclav Dvorak ,  Fred Rennig

IPC: H04L12/40 ,  G06F13/42

CPC classification number: H04L12/40013 ,  G06F13/423 ,  H04L12/40169 ,  H04L2012/40215

Abstract: In an embodiment a method for operating a processing system includes programming, by a microprocessor during a CAN FD Light data transmission phase, a control register of a Serial Peripheral Interface (SPI) communication interface of the processing system in order to activate a master mode; generating, by the microprocessor during the CAN FD Light data transmission phase, a transmission CAN FD Light frame; storing, by the microprocessor during the CAN FD Light data transmission phase, the transmission CAN FD Light frame to a memory; and activating, by the microprocessor during the CAN FD Light data transmission phase a first DMA channel so that the first DMA channel sequentially transfers the transmission CAN FD Light frame from the memory to a transmission shift register in the SPI communication interface.

公开(公告)号：US20230053564A1

公开(公告)日：2023-02-23

申请号：US17814113

申请日：2022-07-21

Applicant: STMicroelectronics Design & Application S.R.O. ,  STMicroelectronics Application GMBH

Inventor： Vaclav Dvorak ,  Fred Rennig

IPC: H04L12/40 ,  G06F13/42

Abstract: In an embodiment a method for operating a processing system includes programming, by a microprocessor during a CAN FD Light data transmission phase, a control register of a Serial Peripheral Interface (SPI) communication interface of the processing system in order to activate a master mode; generating, by the microprocessor during the CAN FD Light data transmission phase, a transmission CAN FD Light frame; storing, by the microprocessor during the CAN FD Light data transmission phase, the transmission CAN FD Light frame to a memory; and activating, by the microprocessor during the CAN FD Light data transmission phase a first DMA channel so that the first DMA channel sequentially transfers the transmission CAN FD Light frame from the memory to a transmission shift register in the SPI communication interface.

公开(公告)号：US10295577B1

公开(公告)日：2019-05-21

申请号：US16202864

申请日：2018-11-28

Applicant: STMicroelectronics Design & Application S.R.O.

Inventor： Sandor Petenyi

IPC: H02M3/158 ,  G01R19/00 ,  G05F1/575 ,  G05F1/56 ,  H02H1/00 ,  H02H9/02 ,  H02M3/156 ,  H02M1/00

Abstract: In an embodiment, a current sense circuit includes a copy transistor having a gate configured to be coupled to a gate of an output transistor, and a drain coupled to an input terminal. The drain of the copy transistor is configured to be coupled to a drain of the output transistor. A first transistor has a current path coupled to a current path of the copy transistor. An error amplifier has a non-inverting input coupled to a source of the copy transistor, an inverting input configured to be coupled to a source of the output transistor, an output coupled to a gate of the first transistor, a positive power supply terminal coupled to the input terminal and a negative power supply terminal coupled to a reference supply terminal. A current-to-voltage converter has an input coupled to the current path of the copy transistor.

公开(公告)号：US09691493B1

公开(公告)日：2017-06-27

申请号：US15244664

申请日：2016-08-23

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics Design & Application S.R.O.

Inventor： Marco Pasotti ,  Fabio De Santis ,  Roberto Bregoli ,  Dario Livornesi ,  Sandor Petenyi

IPC: G11C16/10 ,  G11C16/30 ,  H01L27/11521 ,  G11C16/28 ,  G11C16/04 ,  G11C5/14

CPC classification number: G11C16/30 ,  G05F3/30 ,  G11C5/147 ,  G11C16/0408 ,  G11C16/0433 ,  G11C16/10 ,  G11C16/28 ,  G11C2216/10 ,  H01L27/11521 ,  H01L27/1156 ,  H03F3/45188 ,  H03F3/45475 ,  H03F2200/456 ,  H03F2203/45341 ,  H03F2203/45342 ,  H03F2203/45528 ,  H03F2203/45674 ,  H03F2203/45676

Abstract: A device for generating a reference voltage includes a first non-volatile memory cell provided with a control-gate transistor and a reading transistor. The control-gate transistor includes a gate terminal, a body, a first conduction terminal and a second conduction terminal. The first conduction terminal and the second conduction terminal are connected together to form a control-gate terminal. The reading transistor includes a gate terminal that is connected to the gate terminal of the control-gate transistor to form a floating-gate terminal, a body, a third conduction terminal and a fourth conduction terminal. The device also includes a second, equivalent, memory cell. The source terminal of the first non-volatile memory cell and the source terminal of the second equivalent memory cell are connected together.