-
公开(公告)号：US10720840B2
公开(公告)日：2020-07-21
申请号：US16222557
申请日：2018-12-17
Inventor： Matthieu Thomas , Michele Suraci , Massimo Mazzucco
Abstract: A DC-DC converter circuit including at least: a first step down converter having a first pair of switching devices in a half bridge configuration. A second step down converter includes a second pair of switching devices in a half bridge configuration. The first and second step down converters are connected in parallel to an output node connected to an output coil and receive command signals. A feedback loop includes a synchronization module receiving the gate control signals of high side switching devices and adjusts as a function of the gate control signals a delay in a signal path from the command signal to each gate control signal of the high side switching device to synchronize the gate control signals.
-
公开(公告)号：US20190294572A1
公开(公告)日：2019-09-26
申请号：US16360229
申请日：2019-03-21
Inventor： Fred Rennig , Ludek Beran
IPC: G06F13/362 , G06F13/40
Abstract: A device includes a master device, a set of slave devices and a bus. The master device is configured to transmit first messages carrying a set of operation data message portions indicative of operations for implementation by slave devices of the set of slave devices, and second messages addressed to slave devices in the set of slave devices. The second messages convey identifiers identifying respective ones of the slave devices to which the second messages are addressed requesting respective reactions towards the master device within respective expected reaction intervals. The slave devices are configured to receive the first messages transmitted from the master device, read respective operation data message portions in the set of operation data message portions, implement respective operations as a function of the respective operation data message portions read, and receive the second messages transmitted from the master device.
-
公开(公告)号：US20180342594A1
公开(公告)日：2018-11-29
申请号：US15606778
申请日：2017-05-26
Inventor： Patrik Vacula , Milos Vacula , Vlastimil Kote , Adam Kubacak , Milan Lzicar
IPC: H01L29/423 , H01L27/088 , H01L29/06 , H01L29/40 , H01L29/66 , H01L29/778
Abstract: The present disclosure is directed to a plurality of waffle gate parallel transistors having a shared gate on a surface of a semiconductor substrate. The shared gate has connected channels that form a plurality of squares, lines of each of the squares over the perimeter of a respective source or drain region of the plurality of waffle gate parallel transistors. The shared gate includes squares of a first size and shape and a second size and shape. The squares having the first size and shape are each over a respective source region and the squares having the second size and shape are each over a respective drain region. Each of the squares having a first size and shape share at least one side with one of the squares having the second size and shape.
-
14.发明申请公开(公告)号：US20180063638A1
公开(公告)日：2018-03-01
申请号：US15473812
申请日：2017-03-30
Applicant: STMicroelectronics (Rousset) SAS , STMicroelectronics Design and Application S.R.O. , STMicroelectronics (Alps) SAS
Inventor： Jean Claude Bini , Dragos Davidescu , Igor Cesko , Jonathan Cottinet
CPC classification number: H04R3/005 , G10K11/346 , H04R1/406 , H04R3/04 , H04R19/005 , H04R2201/003 , H04R2430/23
Abstract: Several first digital streams of first digital samples at a first sampling frequency are processed to issue corresponding stream that are converted into second digital streams sampled at a second sampling frequency lower than said first sampling frequency. At least one delay to be applied to at least one first digital stream to satisfy a condition on the second digital streams is determined and applied to at least one first digital stream before converting. The converting operation performed is decimation filtering of the first digital streams. The application of the at least one delay to at least one first steam involves skipping a number of first digital samples in the at least one first digital stream. The number skipped depends on the value of the at least one delay. Samples that are skipped are not delivered for decimation filtering.
-
公开(公告)号：US20170102724A1
公开(公告)日：2017-04-13
申请号：US14881498
申请日：2015-10-13
Inventor： Sandor PETENYI
IPC: G05F1/575
CPC classification number: G05F1/575
Abstract: A voltage regulator includes an input terminal to receive an input voltage, an output terminal to supply an output voltage, a power transistor, a differential amplifier, a driver, a dropout detector and a bias current limiter. The differential amplifier provides a drive signal based on a difference between a voltage reference and a feedback signal corresponding to the output voltage. The driver includes an impedance device, and a driver transistor that receives the drive signal so as to vary a bias current to a control terminal of the power transistor. The dropout detector and the bias current limiter is coupled to the input terminal, the impedance device, and the output terminal and includes first and second transistors coupled together, and a bias current generator coupled to the second transistor.
-
Patent Agency Ranking
16.发明授权Method of preventing inversion of output current flow in a voltage regulator and related voltage regulator 有权防止电压调节器和相关电压调节器中输出电流反转的方法公开(公告)号：US09582017B2
公开(公告)日：2017-02-28
申请号：US14320999
申请日：2014-07-01
Inventor： Sandor Petenyi
CPC classification number: G05F1/625 , G05F1/569 , H02H7/1213 , H02J7/0072
Abstract: The reversal of the flow of output current in a voltage regulator is prevented by equipping the voltage regulator of a regulation transistor controlled by an analog voltage control, having its current terminals connected between the control terminal of the fifth transistor power of the regulator and the power supply line or the common ground node of the regulator. The regulation transistor is configured to provide an electrical path of conduction between the control terminal and the power supply line or the ground node and is controlled by an analog voltage control that varies in a continuous manner between a first level, suitable to extinguish the regulation transistor, and a second level suitable for biasing it in an operating condition of deep conduction, as the difference between the supply voltage and the regulated output voltage approaching an offset voltage.
Abstract translation: 通过装配由模拟电压控制器控制的调节晶体管的电压调节器来防止电压调节器中的输出电流的反转，其电流端子连接在调节器的第五晶体管功率的控制端和电源 供电线路或调节器的公共接地节点。 调节晶体管被配置为提供控制端与电源线或接地节点之间的导通电路，并且通过模拟电压控制来控制，该模拟电压控制以连续的方式在适于熄灭调节晶体管的第一电平之间变化 以及适于在深导通的操作条件下偏置它的第二电平，因为电源电压和调节的输出电压之间的差接近偏移电压。
-
公开(公告)号：US12086008B2
公开(公告)日：2024-09-10
申请号：US17942354
申请日：2022-09-12
Inventor： Jerome Lacan , Remi Collette , Christophe Eva , Milan Komarek
IPC: G06F1/3225 , G06F1/3287 , H03K19/017
CPC classification number: G06F1/3225 , G06F1/3287 , H03K19/01742
Abstract: A system includes a control unit configured to be electrically connected to an input of a memory via a communication interface. The control unit includes a first power supply sector configured to be powered when the control unit is in an operating mode and a second power supply sector configured to be powered when the control unit is in the operating mode and in a low consumption mode. In the first power supply sector, the control unit includes a first configuration circuit operating to configure a polarization value of the input of the memory via the communication interface for the operating mode. In the second power supply sector, the control unit includes a second configuration circuit operating to configure a polarization value of the input of the memory via the communication interface for the low consumption mode.
-
公开(公告)号：US11949243B2
公开(公告)日：2024-04-02
申请号：US17124915
申请日：2020-12-17
Inventor： Michal Toula
Abstract: A method implemented by a wireless charging receiver (RX) includes detecting, by the wireless charging RX, that a voltage potential of an output of a rectifier of the wireless charging RX has met a boost mode threshold; placing, by the wireless charging RX, the rectifier into a boost mode; and detecting, by the wireless charging RX, that the voltage potential of the output of the rectifier of the wireless charging RX has met a specified threshold, and based thereon, negotiating, by the wireless charging RX with a wireless charging transmitter (TX), to initiate a power transfer.
-
公开(公告)号：US11831171B2
公开(公告)日：2023-11-28
申请号：US17838794
申请日：2022-06-13
Inventor： Tomas Teply
IPC: H01M10/44 , H01M10/46 , H02J50/12 , H02J7/02 , H02J50/70 , H02J50/80 , H02J50/00 , H01F38/14 , H01F27/36 , H02J50/40 , H04R1/10 , H01F27/28
CPC classification number: H02J50/12 , H01F27/2885 , H01F27/36 , H01F38/14 , H02J7/02 , H02J50/005 , H02J50/40 , H02J50/70 , H02J50/80 , H04R1/1016 , H04R1/1025 , H04R1/1041 , H04R1/1058 , H04R2420/07
Abstract: A system and method for wireless charging a wireless earbud. The wireless earbud having a body that includes a passive magnetic shield and a coil. The coil is wound around a portion of the body comprising the passive magnetic shielding. The wireless earbud receiving wireless energy in response to the placement of the body within an electromagnetic field, which results in the charging of a battery of the wireless earbud.
-
公开(公告)号：US20230085493A1
公开(公告)日：2023-03-16
申请号：US17942354
申请日：2022-09-12
Inventor： Jerome LACAN , Remi COLLETTE , Christophe EVA , Milan KOMAREK
IPC: G06F1/3225 , G06F1/3287 , H03K19/017
Abstract: A system includes a control unit configured to be electrically connected to an input of a memory via a communication interface. The control unit includes a first power supply sector configured to be powered when the control unit is in an operating mode and a second power supply sector configured to be powered when the control unit is in the operating mode and in a low consumption mode. In the first power supply sector, the control unit includes a first configuration circuit operating to configure a polarization value of the input of the memory via the communication interface for the operating mode. In the second power supply sector, the control unit includes a second configuration circuit operating to configure a polarization value of the input of the memory via the communication interface for the low consumption mode.
-
-
-
-
-
-
-
-
-
Search Results
80
records
(took 0.019 seconds)
