公开(公告)号：US06211031B1

公开(公告)日：2001-04-03

申请号：US09165000

申请日：1998-10-01

申请人： Dah-Chih Lin ,  Chin-Heng Shen ,  Sen-Fu Chen

发明人： Dah-Chih Lin ,  Chin-Heng Shen ,  Sen-Fu Chen

IPC分类号： H01L2120

CPC分类号： H01L28/20 ,  H01L27/0802

摘要： A new method of forming polysilicon resistors having differing resistances using a dual polysilicon process is described. A first polysilicon layer is deposited over a dielectric layer on a semiconductor substrate. The first polysilicon layer is etched away where it is not covered by a mask. Thereafter, a second polysilicon layer is deposited overlying the first polysilicon layer and the dielectric layer. The first and second polysilicon layers are patterned to form a first polysilicon structure comprising the first and second polysilicon layers over the dielectric layer and a second polysilicon structure comprising the second polysilicon layer overlying the dielectric layer. The first and second polysilicon structures are doped to form the first polysilicon structure having a first resistance and the second polysilicon structure having a second resistance wherein the first resistance is lower than the second resistance.

摘要翻译： 描述了使用双重多晶硅工艺形成具有不同电阻的多晶硅电阻器的新方法。 第一多晶硅层沉积在半导体衬底上的电介质层上。 第一多晶硅层被蚀刻掉，其未被掩模覆盖。 此后，沉积覆盖第一多晶硅层和电介质层的第二多晶硅层。 图案化第一和第二多晶硅层以形成第一多晶硅结构，该第一多晶硅结构包括介电层上的第一和第二多晶硅层，以及包括覆盖在电介质层上的第二多晶硅层的第二多晶硅结构。 掺杂第一和第二多晶硅结构以形成具有第一电阻的第一多晶硅结构，并且第二多晶硅结构具有第二电阻，其中第一电阻低于第二电阻。

公开(公告)号：US6143474A

公开(公告)日：2000-11-07

申请号：US73950

申请日：1998-05-07

申请人： Chih-Heng Shen ,  Sen-Fu Chen ,  Huan-Wen Wang ,  Ying-Tzu Yen

发明人： Chih-Heng Shen ,  Sen-Fu Chen ,  Huan-Wen Wang ,  Ying-Tzu Yen

IPC分类号： H01L21/02 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/08 ,  G03F7/00

CPC分类号： H01L21/32137 ,  H01L21/28035 ,  H01L21/32139 ,  H01L21/82345 ,  H01L27/0629 ,  H01L27/0802 ,  H01L27/0805 ,  H01L28/20 ,  H01L28/40

摘要： This method forms structures with different resistance values from a single polysilicon film formed on a substrate. Form a hard masking layer on the polysilicon film. Form a photoresist mask over the hard masking layer. Partially etch the hard masking layer through the photoresist mask to reduce the thickness of the polysilicon while leaving the remainder of the hard masking layer with the original thickness. The thickness is reduced in locations where a low resistance is to be located in the polysilicon film. Then dope the polysilicon layer through the hard masking layer with variable doping as a function of the reduced thickness and the original thickness of the hard masking layer.

摘要翻译： 该方法从形成在基板上的单个多晶硅膜形成具有不同电阻值的结构。 在多晶硅膜上形成硬掩模层。 在硬掩模层上形成光刻胶掩模。 通过光致抗蚀剂掩模部分地蚀刻硬掩模层以减少多晶硅的厚度，同时留下具有原始厚度的硬掩模层的其余部分。 在多晶硅膜中要设置低电阻的位置，厚度减小。 然后通过具有可变掺杂的硬掩模层作为硬掩模层的减小的厚度和原始厚度的函数来掺杂多晶硅层。

公开(公告)号：US6093629A

公开(公告)日：2000-07-25

申请号：US17566

申请日：1998-02-02

申请人： Sen-Fu Chen

发明人： Sen-Fu Chen

IPC分类号： H01L21/285 ,  H01L21/768 ,  H01L21/44

CPC分类号： H01L21/76877 ,  H01L21/28512

摘要： A method for forming n- and p-type contacts for CMOS integrated circuits is described wherein the contact openings are ion implanted after being etched to provide supplemental doping to the exposed device elements in order to secure a reliable low resistance interface with subsequently deposited contact metallurgy The p-type contact openings and the n-type contact openings are patterned, etched, and ion implanted separately, thereby requiring only two photolithographic steps. By etching and implanting the p-contacts and n-contacts separately, the method eliminates one highly complex and contaminative photolithographic step and introduces a less complex etch step with reduced contamination risk, thereby achieving a cost saving by improving yield and reducing process time. It is optional which contacts are processed first.

摘要翻译： 描述了一种用于形成用于CMOS集成电路的n型和p型触点形成的方法，其中在蚀刻后接触开口被离子注入，以向暴露的器件元件提供补充掺杂，以确保可靠的低电阻接口随后沉积的接触冶金 p型接触开口和n型接触开口被分别图案化，蚀刻和离子注入，从而仅需要两个光刻步骤。 通过分别蚀刻和注入p触点和n触点，该方法消除了一个高度复杂和污染的光刻步骤，并引入了较不复杂的蚀刻步骤，降低了污染风险，从而通过提高产量和缩短处理时间来节省成本。 首先处理哪些联系人是可选的。

公开(公告)号：US5719087A

公开(公告)日：1998-02-17

申请号：US612043

申请日：1996-03-07

申请人： Sen Fu Chen ,  Jie Shing Wu ,  Po-Tau Chu ,  Wen-Cheng Chang

发明人： Sen Fu Chen ,  Jie Shing Wu ,  Po-Tau Chu ,  Wen-Cheng Chang

IPC分类号： H01L21/473 ,  H01L21/60 ,  H01L21/44

CPC分类号： H01L21/473 ,  H01L24/11 ,  H01L2224/13099 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01082 ,  H01L2924/14

摘要： A protective cap of dielectric material is deposited by plasma-enhanced chemical vapor deposition on the surface of electrical bonding pads of semiconductor integrated circuits prior to deposition of the final passivation layer. The protective cap serves to isolate the pad surface from electrochemical or other interaction with the etching solution used to open contact holes through the passivation layer. This prevents the formation of surface damage and residues on the pad which lead to yield and reliability problem with integrated circuits.

摘要翻译： 在沉积最终钝化层之前，通过等离子体增强化学气相沉积在半导体集成电路的电接合焊盘的表面上沉积电介质材料的保护帽。 保护盖用于将焊盘表面与用于打开通过钝化层的接触孔的蚀刻溶液的电化学或其它相互作用隔离。 这可以防止表面损伤和焊盘上的残留物的形成，从而导致集成电路的产量和可靠性问题。

公开(公告)号：US06394104B1

公开(公告)日：2002-05-28

申请号：US09144822

申请日：1998-08-28

申请人： Sen-Fu Chen ,  Ming-Chieh Yeh

发明人： Sen-Fu Chen ,  Ming-Chieh Yeh

IPC分类号： B08B900

CPC分类号： C23G5/00 ,  H01J2237/3342 ,  H01L21/02046 ,  Y10S438/905

摘要： A new method for improving particle level, stability of etch rate, and better etch uniformity by using a dry plasma clean to remove polymer buildup from the upper electrode and walls of an etch chamber after spin-on-glass etchback is described. An etching chamber having a lower electrode, upper electrode, and interior walls is provided. Spin-on-glass etchback is performed within the etching chamber whereby a polymer buildup forms on surfaces of chamber. A dummy wafer is placed into the etching chamber and the polymer buildup within the chamber is removed using a dry plasma cleaning process.

摘要翻译： 描述了通过使用干等离子体清洁从旋涂玻璃回蚀之后的蚀刻室的上电极和壁去除聚合物积聚来改进颗粒水平，蚀刻速率的稳定性和更好的蚀刻均匀性的新方法。 提供具有下电极，上电极和内壁的蚀刻室。 在蚀刻室内进行旋转玻璃回蚀，由此在室的表面上形成聚合物积聚。 将伪晶片放置在蚀刻室中，并且使用干等离子体清洁工艺除去室内的聚合物积聚。

公开(公告)号：US06320269B1

公开(公告)日：2001-11-20

申请号：US09304303

申请日：1999-05-03

申请人： Sen-Fu Chen ,  Kuei-Jen Chang

发明人： Sen-Fu Chen ,  Kuei-Jen Chang

IPC分类号： H01L2328

CPC分类号： B24B1/00 ,  B24B7/228 ,  H01L21/76804

摘要： A protective tape is applied to the device side of a wafer (to protect it during an operation to grind the back side of the wafer) after the surface has been prepared to present only sloping surfaces to the tape. This profile prevents the otherwise sharp edges of the holes for the bonding pads from cutting into the adhesive of the tape and causing adhesive particles to remain on the wafer surface after the tape has been removed. Particles of resist can interfere with attaching wires to the bonding pads. The tape receiving surface of the wafer is commonly formed by a passivation layer and by bonding pad sites that are exposed through holes in the passivation layer. These sloping profiles can be formed by giving a sloping profile to the holes in the photoresist before the holes are etched. Alternatively the holes can be etched suitably wider at the top than at the bottom.

摘要翻译： 在制备表面之后，仅将斜面呈现到带上，将保护带施加到晶片的器件侧（以在操作期间保护它以研磨晶片的背面）。 该轮廓防止用于接合垫的孔的另外锐利的边缘切割成带的粘合剂，并且在带被移除之后导致粘合剂颗粒保留在晶片表面上。 抗蚀剂颗粒会干扰连接到焊盘的导线。 晶片的磁带接收表面通常由钝化层和通过钝化层中的孔暴露的焊盘位置形成。 这些倾斜轮廓可以通过在蚀刻孔之前向光致抗蚀剂中的孔赋予倾斜轮廓而形成。 或者，孔可以在顶部比底部适当地更宽。

公开(公告)号：US6077776A

公开(公告)日：2000-06-20

申请号：US40434

申请日：1998-03-18

申请人： Ching-Wen Cho ,  Cheng-Fu Hsu ,  Sen-Fu Chen ,  Po-Tao Chu

发明人： Ching-Wen Cho ,  Cheng-Fu Hsu ,  Sen-Fu Chen ,  Po-Tao Chu

IPC分类号： H01L21/28 ,  H01L21/3105 ,  H01L21/4763

CPC分类号： H01L21/28123 ,  H01L21/28035 ,  H01L21/3105 ,  Y10S438/906

摘要： A new method of removing impurities and moisture from the surface of a wafer and thereby preventing polysilicon residue is described. A dielectric layer is provided over the surface of a semiconductor substrate. A polysilicon layer is deposited overlying the dielectric layer. A hard mask layer is deposited overlying the polysilicon layer and patterned to form a hard mask. The wafer is cleaned whereby moisture and impurities form on the surfaces of the hard mask and the polysilicon layer. Thereafter, the wafer is heat treated whereby the moisture and impurities are removed. Thereafter, the polysilicon layer is etched away where it is not covered by the hard mask to complete formation of a polysilicon line on a wafer in the fabrication of an integrated circuit.

摘要翻译： 描述了从晶片表面去除杂质和水分从而防止多晶硅残渣的新方法。 在半导体衬底的表面上设置电介质层。 沉积覆盖在电介质层上的多晶硅层。 沉积覆盖多晶硅层的硬掩模层并图案化以形成硬掩模。 清洁晶片，从而在硬掩模和多晶硅层的表面上形成水分和杂质。 此后，对晶片进行热处理，除去水分和杂质。 此后，多晶硅层被蚀刻掉，其中它不被硬掩模覆盖，以在集成电路的制造中在晶片上完成多晶硅线的形成。

公开(公告)号：US6071826A

公开(公告)日：2000-06-06

申请号：US249259

申请日：1999-02-12

申请人： Ching-Wen Cho ,  Hua-Yu Yang ,  Sen-Fu Chen ,  Chih-Heng Shen ,  Wen-Cheng Chien ,  Chang-Jen Wu ,  Chi-Hsin Lo ,  Hui-Chen Chu

发明人： Ching-Wen Cho ,  Hua-Yu Yang ,  Sen-Fu Chen ,  Chih-Heng Shen ,  Wen-Cheng Chien ,  Chang-Jen Wu ,  Chi-Hsin Lo ,  Hui-Chen Chu

IPC分类号： H01L21/336 ,  H01L27/146 ,  H01L21/00

CPC分类号： H01L29/6659 ,  H01L27/14601 ,  H01L27/14683

摘要： A method for forming a CMOS image sensor spacer structure. A polysilicon gate electrode is formed on a substrate; a thin layer of first dielectric is deposited over the exposed surfaces of the gate electrode and the top of the substrate. Next a second layer of dielectric is deposited after which etching is performed to create the electrode spacer. The deposited second layer of dielectric serves as an etch stop and prevents damage to the substrate surface between spacers of the gate electrodes. An alternate method uses a thin ply layer as the stop layer and, in so doing, source/drain damage caused by the white pixel problem.

摘要翻译： 一种用于形成CMOS图像传感器间隔结构的方法。 在基板上形成多晶硅栅电极; 第一电介质的薄层沉积在栅电极和衬底的顶部的暴露表面上。 接下来，沉积第二层电介质，之后进行蚀刻以形成电极间隔物。 沉积的第二介电层用作蚀刻停止层并且防止对栅电极的间隔物之间​​的衬底表面的损坏。 一种替代方法是使用薄层层作为停止层，并且在这样做时，由白色像素问题引起的源/漏损坏。