公开(公告)号：US20100060320A1

公开(公告)日：2010-03-11

申请号：US12209051

申请日：2008-09-11

Applicant: Seong-Hoon Lee

Inventor： Seong-Hoon Lee

IPC: H03K19/0185 ,  G11C7/10

CPC classification number: G11C7/1051 ,  G11C7/1057 ,  G11C8/06 ,  G11C8/08 ,  H03K19/018521

Abstract: Processor-based systems, memories, signal driver circuits, and methods of generating an output signal are disclosed. One such signal driver circuit includes a signal driver configured to generate an output signal at an output node in response to an input signal and a transistor coupled to the signal driver that is configured to couple and decouple the output node and the voltage supply according to a control signal. A voltage comparator circuit coupled to the output node and the transistor is configured to generate the control signal to control coupling and decoupling of the output node and the voltage supply through the transistor based on a voltage of the output signal relative to the reference voltage.

Abstract translation: 公开了基于处理器的系统，存储器，信号驱动器电路和产生输出信号的方法。 一个这样的信号驱动器电路包括信号驱动器，其被配置为响应于输入信号在输出节点处产生输出信号，以及耦合到信号驱动器的晶体管，其被配置为根据输出信号耦合和去耦输出节点和电压源 控制信号。 耦合到输出节点和晶体管的电压比较器电路被配置为产生控制信号，以基于输出信号相对于参考电压的电压来控制输出节点和通过晶体管的电压源的耦合和去耦。

公开(公告)号：US07619449B2

公开(公告)日：2009-11-17

申请号：US11759782

申请日：2007-06-07

Applicant: Seong Hoon Lee

Inventor： Seong Hoon Lee

IPC: H03L7/00 ,  G06F1/12

CPC classification number: H03L7/07 ,  G06F1/10 ,  H03L7/0814

Abstract: Circuits, methods and systems are disclosed providing clock synchronization circuits for synchronized clock distribution for a plurality of devices in a semiconductor device. The clock synchronization apparatus includes an independent synchronization circuit and a dependent synchronization circuit. The independent synchronization circuit may provide synchronized clock distribution for a first destination while the dependent synchronization circuit may provide synchronized clock distribution to a second destination. A method for synchronized clock distribution to a plurality of destinations is also described.

Abstract translation: 公开了提供用于半导体器件中的多个器件的同步时钟分配的时钟同步电路的电路，方法和系统。 时钟同步装置包括独立同步电路和从属同步电路。 独立同步电路可以为第一目的地提供同步的时钟分配，而从属同步电路可以向第二目的地提供同步的时钟分配。 还描述了用于向多个目的地分配时钟的方法。

公开(公告)号：US20090256592A1

公开(公告)日：2009-10-15

申请号：US12101770

申请日：2008-04-11

Applicant: Seong-Hoon Lee

Inventor： Seong-Hoon Lee

IPC: H03K19/094 ,  H03K19/0175

CPC classification number: G11C5/147 ,  H02M3/1563 ,  H03K17/687 ,  H03K19/018507 ,  H03K19/018585

Abstract: A signal driver circuit having an adjustable output voltage for a high-logic level output signal. The signal driver circuit includes a signal driver configured to output a first logic level signal having a first voltage and output a second logic level signal having a second voltage according to an input signal. A voltage controlled voltage supply coupled to the signal driver provides the first voltage for the first logic level signal. The magnitude of the first voltage provided by the voltage controlled voltage supply is based on a bias voltage. A bias voltage generator can be coupled to the voltage controlled voltage supply to provide the bias voltage.

Abstract translation: 具有用于高逻辑电平输出信号的可调输出电压的信号驱动器电路。 信号驱动器电路包括：信号驱动器，被配置为输出具有第一电压的第一逻辑电平信号，并输出具有根据输入信号的第二电压的第二逻辑电平信号。 耦合到信号驱动器的电压控制电压电源为第一逻辑电平信号提供第一电压。 由压控电压提供的第一电压的大小基于偏置电压。 偏置电压发生器可以耦合到压控电压源以提供偏置电压。

公开(公告)号：US20080309377A1

公开(公告)日：2008-12-18

申请号：US11762557

申请日：2007-06-13

Applicant: Seong-Hoon Lee

Inventor： Seong-Hoon Lee

IPC: H03D13/00

CPC classification number: H03D13/004

Abstract: Methods and apparatus are disclosed, such as those involving a digital phase detector that includes a phase detection circuit configured to detect which one of two clock signals leads the other. One such phase detector includes a balancer configured to prepare the phase detection circuit for a phase detection. The phase detection circuit of one or more embodiments includes a cross-coupled latch configured to receive the two clock signals and generate a first latch output and a second latch output in response to the two clock signals. The aforementioned balancer is configured to substantially equalize the voltage levels of the first and second latch outputs before the phase detection circuit detects a phase difference between the two clock signals. For example, the balancer might pre-charge the outputs of the phase detection circuit to substantially the same voltage level before phase detection.

Abstract translation: 公开了诸如涉及数字相位检测器的方法和装置，该数字相位检测器包括被配置为检测两个时钟信号中的哪一个引导另一个的相位检测电路。 一个这样的相位检测器包括配置成准备用于相位检测的相位检测电路的平衡器。 一个或多个实施例的相位检测电路包括交叉耦合锁存器，其被配置为接收两个时钟信号，并响应于两个时钟信号产生第一锁存器输出和第二锁存器输出。 上述平衡器被配置为在相位检测电路检测到两个时钟信号之间的相位差之前基本均衡第一和第二锁存器输出的电压电平。 例如，平衡器可以在相位检测之前将相位检测电路的输出预充电至基本相同的电压电平。

公开(公告)号：US07423463B2

公开(公告)日：2008-09-09

申请号：US11489693

申请日：2006-07-18

Applicant: Adrian J Drexler ,  Debra M Bell ,  Tyler J Gomm ,  Seong-hoon Lee

Inventor： Adrian J Drexler ,  Debra M Bell ,  Tyler J Gomm ,  Seong-hoon Lee

IPC: H03L7/06

CPC classification number: H03L7/08 ,  G11C7/22 ,  G11C7/222 ,  H03L7/0812

Abstract: Clock capturing synchronization circuitry first generates a synchronized clock signal from a reference clock signal, then captures the synchronized clock signal, and continues to output a synchronized clock signal after the reference clock signal is removed. The clock capturing synchronization circuitry also reduces input referred jitter in the synchronized clock signal.

公开(公告)号：US07372310B2

公开(公告)日：2008-05-13

申请号：US11195154

申请日：2005-08-01

Applicant: Seong-Hoon Lee

Inventor： Seong-Hoon Lee

IPC: H03L7/06

CPC classification number: H03L7/18 ,  H03L7/089 ,  H03L7/0997 ,  H03L7/0998

Abstract: Digital delay-locked loops (DLLs) and methods are provided for signal frequency multiplication. Analog delay elements of typical frequency-multiplying DLLs are replaced with digital and digitally-controlled elements including a variable delay line. The number of unit delay elements in the delay line can be selected to produce a desired output signal delay. Phase-mixing of multiple variable delay line outputs achieves finer delay-time adjustments.

Abstract translation: 数字延迟锁定环（DLL）和方法用于信号倍频。 典型倍频DLL的模拟延迟元件由包括可变延迟线的数字和数字控制元件代替。 可以选择延迟线中的单位延迟元件的数量以产生期望的输出信号延迟。 多个可变延迟线输出的相位混合实现更精细的延迟时间调整。

公开(公告)号：US07355464B2

公开(公告)日：2008-04-08

申请号：US11124743

申请日：2005-05-09

Applicant: Seong-Hoon Lee

Inventor： Seong-Hoon Lee

IPC: H03L7/06

CPC classification number: H03L7/0812 ,  H03L7/089 ,  H03L7/0891 ,  H03L7/10

Abstract: A method and circuitry for a Delay Locked Loop (DLL) or a phase Locked Loop (PLL) is disclosed, which improves the loop stability at high frequencies and allows maximum tracking bandwidth, regardless of process, voltage, or temperature variations. Central to the technique is to effectively operate the loop at a lower frequency close to its own intrinsic bandwidth (1/tLoop) instead of at the higher frequency of the clock signal (1/tCK). To do so, in one embodiment, the loop delay, tLoop, is measured or estimated prior to operation of the loop. The phase detector is then enabled to operate close to the loop frequency, 1/tLoop. In short, the phase detector is made not to see activity during useless delay times, which prevents the loop from overreacting and becoming unstable.

Abstract translation: 公开了用于延迟锁定环（DLL）或锁相环（PLL）的方法和电路，其改善了高频下的环路稳定性，并允许最大跟踪带宽，而不管过程，电压或温度变化。 该技术的核心是以更接近其自身固有带宽（1 / tLoop）的较低频率有效地操作环路，而不是在时钟信号（1 / tCK）的较高频率处。 为了做到这一点，在一个实施例中，在循环操作之前测量或估计环路延迟t L oop。 然后，相位检测器使能接近环路频率1 / tLoop。 简而言之，使相位检测器在无用的延迟时间期间看不到活动，从而防止环路过度反应并变得不稳定。

公开(公告)号：US07336548B2

公开(公告)日：2008-02-26

申请号：US11542918

申请日：2006-10-03

Applicant: Seong-Hoon Lee

Inventor： Seong-Hoon Lee

IPC: G11C7/00

CPC classification number: G11C7/1072 ,  G11C7/222 ,  H03L7/0812 ,  H03L7/095 ,  H03L7/0995

Abstract: A clock generating circuit includes a phase comparison circuit that generates a delay control signal corresponding to the relative phases of an output clock signal and a reference clock signal. A voltage controlled delay circuit generates the delayed clock signal by inverting a signal applied to its input and delaying the signal by a delay that is determined by a delay control signal. A selection circuit couples either the reference clock signal or the delayed clock signal to the input of the voltage controlled delay circuit. When the reference clock signal is coupled to the input of the voltage controlled delay circuit, the clock generating circuit functions as a delay-lock loop. When the delayed clock signal is coupled to the input of the voltage controlled delay circuit, the voltage controlled delay circuit operates as a ring oscillator so that the clock generating circuit functions as a phase-lock loop.

Abstract translation: 时钟发生电路包括相位比较电路，其产生对应于输出时钟信号和参考时钟信号的相对相位的延迟控制信号。 电压控制延迟电路通过反相施加到其输入的信号并延迟由延迟控制信号确定的延迟来产生延迟的时钟信号。 选择电路将参考时钟信号或延迟时钟信号耦合到电压控制延迟电路的输入端。 当参考时钟信号耦合到电压控制延迟电路的输入时，时钟发生电路用作延迟锁定环路。 当延迟时钟信号耦合到电压控制延迟电路的输入端时，电压控制延迟电路作为环形振荡器工作，使得时钟发生电路用作锁相环。

公开(公告)号：US07251194B2

公开(公告)日：2007-07-31

申请号：US11352078

申请日：2006-02-10

Applicant: Feng Lin ,  Brent Keeth ,  Brian Johnson ,  Seong-hoon Lee

Inventor： Feng Lin ,  Brent Keeth ,  Brian Johnson ,  Seong-hoon Lee

IPC: G11C8/18

CPC classification number: G11C7/109 ,  G11C7/1006 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/22 ,  G11C7/222

Abstract: A memory system couples command, address or write data signals from a memory controller to a memory device and read data signals from the memory device to the memory controller. A respective strobe generator circuit in each of the memory controller and the memory device each generates an in-phase strobe signal and a quadrature strobe signal. Command, address or write data signals stored in respective output latches in the memory controller are clocked by the in-phase signals from the internal strobe generator circuit. These command, address or write data signals are latched into input latches in the memory device by the quadrature strobe signal coupled from the memory controller to the memory device. In substantially the same manner, read data signals are coupled from the memory device to the memory controller using the in-phase and quadrature strobe signals generated by the internal strobe generator circuit.

Abstract translation: 存储器系统将命令，地址或写入数据信号从存储器控制器耦合到存储器件，并将数据信号从存储器件读取到存储器控制器。 每个存储器控制器和存储器件中的相应选通发生器电路都产生同相选通信号和正交选通信号。 存储在存储器控制器中的相应输出锁存器中的命令，地址或写入数据信号由来自内部选通发生器电路的同相信号计时。 这些命令，地址或写入数据信号通过从存储器控制器耦合到存储器件的正交选通信号而被锁存在存储器件中的输入锁存器中。 以基本相同的方式，使用由内部选通发生器电路产生的同相和正交选通信号，将读取的数据信号从存储器件耦合到存储器控制器。

公开(公告)号：US07230495B2

公开(公告)日：2007-06-12

申请号：US10834775

申请日：2004-04-28

Applicant: Seong-hoon Lee ,  Feng Lin

Inventor： Seong-hoon Lee ,  Feng Lin

IPC: H03L7/00

CPC classification number: H03L7/10 ,  H03L7/083 ,  H03L7/0891 ,  H03L7/0995

Abstract: PLL circuits are provided in which a voltage-controlled oscillator (VCO) comprising one or more voltage-controlled delay units (VCDs) is initialized with the control voltage of a voltage-controlled delay line (VCDL) having substantially identical VCDs. In general, VCDLs provide for faster signal locking than do VCOs. The VCO locks to a frequency of a reference signal at substantially the same time that the VCDL locks to the reference signal. Lock time of the PLL circuit is thereby reduced. A timing circuit prevents the VCO control voltage from being adjusted during phase locking of the VCO. This allows the VCO frequency lock to be maintained during the VCO phase locking. Lock time is thereby further reduced. The timing circuit locks the VCO to a phase of the reference signal by restarting oscillation of the VCO at an appropriate time.

Abstract translation: 提供PLL电路，其中包括一个或多个电压控制延迟单元（VCD）的压控振荡器（VCO）用具有基本相同的VCD的电压控制延迟线（VCDL）的控制电压来初始化。 通常，VCDLs比VCO提供更快的信号锁定。 在与VCDL锁定到参考信号的基本相同的时刻，VCO锁定到参考信号的频率。 因此PLL电路的锁定时间减少。 定时电路防止在VCO的锁相期间调节VCO控制电压。 这允许在VCO锁相期间保持VCO频率锁定。 从而进一步减少锁定时间。 定时电路通过在适当的时间重新启动VCO的振荡将VCO锁定到参考信号的相位。