公开(公告)号：US20120299125A1

公开(公告)日：2012-11-29

申请号：US13568832

申请日：2012-08-07

Applicant: Dechao Guo ,  Wilfried E.A. Haensch ,  Shu-Jen Han ,  Chung-Hsun Lin

Inventor： Dechao Guo ,  Wilfried E.A. Haensch ,  Shu-Jen Han ,  Chung-Hsun Lin

IPC: H01L29/78

CPC classification number: H01L21/28008 ,  H01L21/28052 ,  H01L21/28097 ,  H01L21/76897 ,  H01L29/517 ,  H01L29/66507 ,  H01L29/66545

Abstract: A method of forming a gate structure with a self-aligned contact is provided and includes sequentially depositing a sacrificial layer and a secondary layer onto poly-Si disposed at a location of the gate structure, encapsulating the sacrificial layer, the secondary layer and the poly-Si, removing the sacrificial layer through openings formed in the secondary layer and forming silicide within at least the space formally occupied by the sacrificial layer.

Abstract translation: 提供了一种形成具有自对准接触的栅极结构的方法，并且包括将牺牲层和次级层顺序地沉积到设置在栅极结构的位置处的多晶硅上，封装牺牲层，第二层和聚 -Si，通过形成在次级层中的开口去除牺牲层，并在至少由牺牲层正式占据的空间内形成硅化物。

公开(公告)号：US20120248509A1

公开(公告)日：2012-10-04

申请号：US13075443

申请日：2011-03-30

Applicant: Dechao GUO ,  Shu-Jen HAN ,  Keith Kwong Hon WONG ,  Jun YUAN

Inventor： Dechao GUO ,  Shu-Jen HAN ,  Keith Kwong Hon WONG ,  Jun YUAN

IPC: H01L29/772 ,  H01L21/28

CPC classification number: H01L29/4966 ,  H01L29/66545 ,  H01L29/7843

Abstract: Processes for metal fill in replacement metal gate integration schemes and resultant devices are provided herein. The method includes forming a dummy gate on a semiconductor substrate. The dummy gate includes forming a metal layer between a first material and a second material. The method further includes partially removing the dummy gate to form an opening bounded by a spacer material. The method further includes forming a recess in the spacer material to widen a portion of the opening. The method further includes removing a remaining portion of the dummy gate through the opening to form a trench having the recess forming an upper portion thereof. The method further includes filling the trench and the recess with a replacement metal gate stack.

Abstract translation: 本文提供了用于替换金属栅极集成方案和所得器件的金属填充工艺。 该方法包括在半导体衬底上形成虚拟栅极。 虚拟门包括在第一材料和第二材料之间形成金属层。 该方法还包括部分地去除伪栅极以形成由间隔物材料限定的开口。 该方法还包括在间隔物材料中形成凹槽以加宽开口的一部分。 该方法还包括通过开口去除虚拟栅极的剩余部分以形成具有形成其上部的凹部的沟槽。 该方法还包括用替换的金属栅极堆叠填充沟槽和凹部。

公开(公告)号：US20120248502A1

公开(公告)日：2012-10-04

申请号：US13074878

申请日：2011-03-29

Applicant: Cheng-Wei Cheng ,  Shu-Jen Han ,  Ko-Tao Lee ,  Kuen-Ting Shiu

Inventor： Cheng-Wei Cheng ,  Shu-Jen Han ,  Ko-Tao Lee ,  Kuen-Ting Shiu

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7781 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/41725 ,  H01L29/66462 ,  H01L29/78681

Abstract: Field Effect Transistors (FETs), Integrated Circuit (IC) chips including the FETs, and a method of forming the FETs and IC. FET locations define FET pedestals on a layered semiconductor wafer that may include a III-V semiconductor surface layer, e.g., Gallium Arsenide (GaAs), and a buried layer, e.g., Aluminum Arsenide (AlAs). A dielectric material, e.g., Aluminum Oxide (AlO), surrounds pedestals at least in FET source/drain regions. A conductive cap caps channel sidewalls at opposite channel ends. III-V on insulator (IIIVOI) devices form wherever the dielectric material layer is thicker than half the device length. Source/drain contacts are formed to the caps and terminate in/above the dielectric material in the buried layer.

Abstract translation: 场效应晶体管（FET），包括FET的集成电路（IC）芯片，以及形成FET和IC的方法。 FET位置在可以包括III-V半导体表面层（例如砷化镓（GaAs））和掩埋层（例如AlAs）的分层半导体晶片上限定FET基座。 介电材料，例如氧化铝（AlO），至少在FET源极/漏极区域中围绕基座。 导电盖帽在相对的通道端部封闭通道侧壁。 绝缘体上的III-V（IIIVOI）器件形成电介质材料层的厚度超过器件长度的一半。 源极/漏极触点形成到盖并终止在掩埋层中的介电材料之中/之上。

公开(公告)号：US20120175594A1

公开(公告)日：2012-07-12

申请号：US12986342

申请日：2011-01-07

Applicant: Zhihong Chen ,  Aaron Daniel Franklin ,  Shu-Jen Han

Inventor： Zhihong Chen ,  Aaron Daniel Franklin ,  Shu-Jen Han

IPC: H01L29/15 ,  H01L21/336

CPC classification number: H01L29/66045 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02527 ,  H01L21/044 ,  H01L29/1606 ,  H01L29/42376 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/4916 ,  H01L29/517 ,  H01L29/66015 ,  H01L29/66742 ,  H01L29/78645 ,  H01L29/78648 ,  H01L29/78684

Abstract: An electronic device comprises an insulator, a local first gate embedded in the insulator with a top surface of the first gate being substantially coplanar with a surface of the insulator, a first dielectric layer formed over the first gate and insulator, and a channel. The channel comprises a bilayer graphene layer formed on the first dielectric layer. The first dielectric layer provides a substantially flat surface on which the channel is formed. A second dielectric layer formed over the bilayer graphene layer and a local second gate formed over the second dielectric layer. Each of the local first and second gates is capacitively coupled to the channel of the bilayer graphene layer. The local first and second gates form a first pair of gates to locally control a first portion of the bilayer graphene layer.

Abstract translation: 电子设备包括绝缘体，嵌入在绝缘体中的局部第一栅极，第一栅极的顶表面与绝缘体的表面基本共面;形成在第一栅极和绝缘体上的第一介电层，以及沟道。 通道包括形成在第一介电层上的双层石墨烯层。 第一电介质层提供基本上平坦的表面，在其上形成沟道。 形成在双层石墨烯层上的第二介电层和在第二介电层上形成的局部第二栅极。 局部第一和第二栅极中的每一个电容耦合到双层石墨烯层的沟道。 局部第一和第二栅极形成第一对栅极以局部控制双层石墨烯层的第一部分。

公开(公告)号：US20120146001A1

公开(公告)日：2012-06-14

申请号：US13401967

申请日：2012-02-22

Applicant: Zhihong Chen ,  Dechao Guo ,  Shu-Jen Han ,  Kai Zhao

Inventor： Zhihong Chen ,  Dechao Guo ,  Shu-Jen Han ,  Kai Zhao

IPC: H01L29/78 ,  B82Y99/00

CPC classification number: H01L29/1606 ,  H01L29/4908 ,  H01L29/66742 ,  H01L29/7781 ,  H01L29/78684

Abstract: A carbon-based field effect transistor (FET) includes a substrate; a carbon layer located on the substrate, the carbon layer comprising a channel region, and source and drain regions located on either side of the channel region; a gate electrode located on the channel region in the carbon layer, the gate electrode comprising a first dielectric layer, a gate metal layer located on the first dielectric layer, and a nitride layer located on the gate metal layer; and a spacer comprising a second dielectric layer located adjacent to the gate electrode, wherein the spacer is not located on the carbon layer.

Abstract translation: 碳基场效应晶体管（FET）包括基板; 位于所述基板上的碳层，所述碳层包括沟道区，以及位于所述沟道区两侧的源区和漏区; 位于所述碳层中的沟道区上的栅电极，所述栅电极包括第一电介质层，位于所述第一电介质层上的栅极金属层和位于所述栅极金属层上的氮化物层; 以及间隔件，其包括邻近所述栅电极的第二电介质层，其中所述间隔物不位于所述碳层上。

公开(公告)号：US08193032B2

公开(公告)日：2012-06-05

申请号：US12826221

申请日：2010-06-29

Applicant: Zhihong Chen ,  Dechao Guo ,  Shu-jen Han ,  Kai Zhao

Inventor： Zhihong Chen ,  Dechao Guo ,  Shu-jen Han ,  Kai Zhao

IPC: H01L21/00

CPC classification number: H01L29/1606 ,  H01L29/4908 ,  H01L29/66742 ,  H01L29/7781 ,  H01L29/78684

Abstract: A method for formation of a carbon-based field effect transistor (FET) includes depositing a first dielectric layer on a carbon layer located on a substrate; forming a gate electrode on the first dielectric layer; etching an exposed portion of the first dielectric layer to expose a portion of the carbon layer; depositing a second dielectric layer over the gate electrode to form a spacer, wherein the second dielectric layer is deposited by atomic layer deposition (ALD), and wherein the second dielectric layer does not form on the exposed portion of the carbon layer; forming source and drain contacts on the carbon layer and forming a gate contact on the gate electrode to form the carbon-based FET.

Abstract translation: 一种用于形成碳基场效应晶体管（FET）的方法包括：在位于衬底上的碳层上沉积第一介电层; 在所述第一电介质层上形成栅电极; 蚀刻第一介电层的暴露部分以暴露碳层的一部分; 在所述栅电极上沉积第二电介质层以形成间隔物，其中所述第二电介质层通过原子层沉积（ALD）沉积，并且其中所述第二电介质层不在所述碳层的暴露部分上形成; 在碳层上形成源极和漏极接触，并在栅电极上形成栅极接触以形成碳基FET。

公开(公告)号：US20120032149A1

公开(公告)日：2012-02-09

申请号：US12850095

申请日：2010-08-04

Applicant: Zhihong Chen ,  Aaron Daniel Franklin ,  Shu-Jen Han

Inventor： Zhihong Chen ,  Aaron Daniel Franklin ,  Shu-Jen Han

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L51/0048 ,  B82Y10/00 ,  H01L51/0558 ,  Y10S977/742 ,  Y10S977/938

Abstract: Transistor devices having vertically stacked carbon nanotube channels and techniques for the fabrication thereof are provided. In one aspect, a transistor device is provided. The transistor device includes a substrate; a bottom gate embedded in the substrate with a top surface of the bottom gate being substantially coplanar with a surface of the substrate; a stack of device layers on the substrate over the bottom gate, wherein each of the device layers in the stack includes a first dielectric, a carbon nanotube channel on the first dielectric, a second dielectric on the carbon nanotube channel and a top gate on the second dielectric; and source and drain contacts that interconnect the carbon nanotube channels in parallel. A method of fabricating a transistor device is also provided.

Abstract translation: 提供具有垂直堆叠的碳纳米管通道的晶体管器件及其制造技术。 一方面，提供一种晶体管器件。 晶体管器件包括衬底; 嵌入基板中的底栅与底栅的顶表面基本上与基板的表面共面; 在底栅上的衬底上的一叠器件层，其中堆叠中的每个器件层包括第一电介质，第一电介质上的碳纳米管通道，碳纳米管通道上的第二电介质和 第二电介质; 以及并联连接碳纳米管通道的源极和漏极触点。 还提供了一种制造晶体管器件的方法。

公开(公告)号：US20110227043A1

公开(公告)日：2011-09-22

申请号：US12727434

申请日：2010-03-19

Applicant: Dechao Guo ,  Shu-Jen Han ,  Chung-Hsun Lin ,  Ning Su

Inventor： Dechao Guo ,  Shu-Jen Han ,  Chung-Hsun Lin ,  Ning Su

IPC: H01L29/786 ,  H01L21/336

CPC classification number: G01N27/4145 ,  G01N27/4146 ,  H01L29/1606 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66742 ,  H01L29/78684 ,  H01L51/0048

Abstract: A method for forming a sensor includes forming a channel in substrate, forming a sacrificial layer in the channel, forming a sensor having a first dielectric layer disposed on the substrate, a graphene layer disposed on the first dielectric layer, and a second dielectric layer disposed on the graphene layer, a source region, a drain region, and a gate region, wherein the gate region is disposed on the sacrificial layer removing the sacrificial layer from the channel.

Abstract translation: 一种用于形成传感器的方法，包括在衬底中形成通道，在通道中形成牺牲层，形成具有设置在衬底上的第一介电层的传感器，设置在第一电介质层上的石墨烯层，以及设置在第二电介质层 在石墨烯层上，源区域，漏极区域和栅极区域，其中栅极区域设置在牺牲层上，从沟道去除牺牲层。

公开(公告)号：US20110049624A1

公开(公告)日：2011-03-03

申请号：US12548005

申请日：2009-08-26

Applicant: Dechao Guo ,  Shu-Jen Han ,  Chung-Hsun Lin ,  Ning Su

Inventor： Dechao Guo ,  Shu-Jen Han ,  Chung-Hsun Lin ,  Ning Su

IPC: H01L29/786 ,  H01L21/336

CPC classification number: H01L21/84 ,  H01L29/41733 ,  H01L29/458 ,  H01L29/66772 ,  H01L29/7839 ,  H01L29/78624

Abstract: A semiconductor device is disclosed that includes a silicon-on-insulator substrate including a buried insulator layer and an overlying semiconductor layer. Source extension and drain extension regions are formed in the semiconductor layer. A deep drain region and a deep source region are formed in the semiconductor layer. A first metal-semiconductor alloy contact layer is formed using tilted metal formation at an angle tilted towards the source extension region, such that the source extension region has a metal-semiconductor alloy contact that abuts the substrate from the source side, as a Schottky contact therebetween and the gate shields metal deposition from abutting the deep drain region. A second metal-semiconductor alloy contact is formed located on the first metal-semiconductor layer on each of the source extension region and drain extension region.

Abstract translation: 公开了一种半导体器件，其包括绝缘体上硅衬底，其包括掩埋绝缘体层和上覆半导体层。 在半导体层中形成源延伸和漏扩展区。 在半导体层中形成深漏极区域和深源极区域。 第一金属 - 半导体合金接触层使用倾斜的金属形成，以朝向源延伸区域倾斜的角度形成，使得源极延伸区域具有金属 - 半导体合金接触件，其从源极侧邻接衬底，作为肖特基接触 并且栅极屏蔽金属沉积物抵靠深漏极区域。 在源极延伸区域和漏极延伸区域中的每一个上，在第一金属 - 半导体层上形成第二金属 - 半导体合金接触。

公开(公告)号：US09102540B2

公开(公告)日：2015-08-11

申请号：US13310194

申请日：2011-12-02

Applicant: Ali Afzali-Ardakani ,  Shu-jen Han ,  Amal Kasry ,  Ahmed Maarouf ,  Glenn J. Martyna ,  Razvan Nistor ,  Hsinyu Tsai

Inventor： Ali Afzali-Ardakani ,  Shu-jen Han ,  Amal Kasry ,  Ahmed Maarouf ,  Glenn J. Martyna ,  Razvan Nistor ,  Hsinyu Tsai

IPC: B82Y30/00 ,  C01B31/04 ,  B82Y40/00 ,  G01N33/543

CPC classification number: G01N33/531 ,  B82Y30/00 ,  B82Y40/00 ,  C01B32/194 ,  G01N33/5308 ,  G01N33/54373 ,  G01N33/54393 ,  G01N33/551 ,  G01N2400/00 ,  H01L21/30

Abstract: A graphene nanomesh based charge sensor and method for producing a graphene nanomesh based charge sensor. The method includes generating multiple holes in graphene in a periodic way to create a graphene nanomesh with a patterned array of multiple holes, passivating an edge of each of the multiple holes of the graphene nanomesh to allow for functionalization of the graphene nanomesh, and functionalizing the passivated edge of each of the multiple holes of the graphene nanomesh with a chemical compound that facilitates chemical binding of a receptor of a target molecule to the edge of one or more of the multiple holes, allowing the target molecule to bind to the receptor, causing a charge to be transferred to the graphene nanomesh to produce a graphene nanomesh based charge sensor for the target molecule.

Abstract translation: 一种基于石墨烯纳米薄膜的电荷传感器和用于生产基于石墨烯纳米薄膜的电荷传感器的方法。 该方法包括以周期性方式在石墨烯中产生多个孔以产生具有多个孔的图案化阵列的石墨烯纳米粒子，钝化石墨烯纳米粒子的多个孔中的每一个的边缘以允许石墨烯纳米粒子的官能化，并使 石墨烯纳米粒子的多个孔的每个的钝化边缘具有促进靶分子的受体与多个孔中的一个或多个的边缘的化学结合的化学化合物，允许靶分子结合受体，导致 将转移到石墨烯纳米片上的电荷以产生用于靶分子的基于石墨烯纳米膜的电荷传感器。