公开(公告)号：US4361814A

公开(公告)日：1982-11-30

申请号：US191545

申请日：1980-09-29

Applicant: Sidney I. Soclof ,  Michael T. Elliott

Inventor： Sidney I. Soclof ,  Michael T. Elliott

IPC: H03F7/00 ,  H03F7/04 ,  H01S4/00 ,  H03F3/10

CPC classification number: H03F7/04

Abstract: A parametric amplifier including a semiconductor body portion (10) comprising a plurality of zones (11,13,15, . . . ) of a first conductivity type, each of the zones having a thickness less than or equal to the Debye length in the semiconductor body portion (11,13,15, . . . ), each of the zones being separated from one another by corresponding insulating layers (12,14, . . . ). The body portion has a first edge portion abutting a first edge of the plurality of zones, and a second edge portion abutting a second edge of the plurality of zones spaced apart from said first edge.A first interface (20) is provided adjacent the first edge portion for transmitting an electromagnetic wave into the semiconductor body portion for propagation therein; and a second interface (21) is provided adjacent the second edge portion for receiving an electromagnetic wave propagating in the body portion.

Abstract translation: 一种参数放大器，包括半导体本体部分（10），该半导体主体部分（10）包括第一导电类型的多个区域（11,13,15，...），每个区域具有小于或等于所述第二导电类型的德拜长度的厚度 半导体主体部分（11,13,15，...），每个区域通过相应的绝缘层（12,14 ...）彼此分离。 主体部分具有邻接多个区域的第一边缘的第一边缘部分和与第一边缘间隔开的多个区域中的第二边缘邻接的第二边缘部分。 第一接口（20）设置成与第一边缘部分相邻，用于将电磁波传输到半导体本体部分中以在其中传播; 并且第二接口（21）设置成与第二边缘部分相邻，用于接收在主体部分中传播的电磁波。

公开(公告)号：US5097316A

公开(公告)日：1992-03-17

申请号：US68383

申请日：1987-06-11

Applicant: Sidney I. Soclof

Inventor： Sidney I. Soclof

IPC: H01L21/265 ,  H01L21/762 ,  H01L21/8222 ,  H01L27/07 ,  H01L27/102 ,  H01L29/735 ,  H01L29/72 ,  H01L29/06

CPC classification number: H01L29/735 ,  H01L21/26586 ,  H01L21/76237 ,  H01L21/8222 ,  H01L27/0727 ,  H01L27/1024

Abstract: The invention is a pair of complementary transistors or arrays thereof and method for producing same in sub-micron dimensions on a silicon substrate selectively doped P and N type by forming intersecting slots in spaced apart relation across the P substrate regions to define semi-arrays of V shaped intermediate regions which will become transistors. Silicon oxide fills these slots and separates the NPN transistor regions from the substrate. Orthogonal slots devide the semi-arrays into individual transistor active regions which are doped N and introduced into each active regions via the orthogonal slots and driven in to comprise the emitter and collector regions on respective sides of original substrate comprising the base regions. The same construction obtains in the N substrate regions to form the arrays of PNP transistors. Metallization patterns complete electrical interconnections to the emitter, base and collector regions and silicon oxide substantially covers the periphery of each active region for total isolation.

Abstract translation: 本发明是一对互补晶体管或其阵列，以及通过在P衬底区域上以间隔开的关系形成跨越P衬底区域的相交槽来在硅衬底上制造选择性掺杂P和N型的亚微米尺寸的方法，以限定半阵列 将成为晶体管的V形中间区域。 氧化硅填充这些槽并将NPN晶体管区域与衬底分离。 正交槽将半阵列分配成单独的晶体管有源区，其被掺杂N并且经由正交槽被引入每个有源区并被驱动以在包括基极区的原始衬底的相应侧上包括发射极和集电极区。 在N个衬底区域中获得相同的结构以形成PNP晶体管阵列。 金属化图案完全与发射极，基极和集电极区的电互连，氧化硅基本上覆盖每个有源区的周边以进行完全隔离。

公开(公告)号：US5047828A

公开(公告)日：1991-09-10

申请号：US66663

申请日：1987-06-24

Applicant: Sidney I. Soclof

Inventor： Sidney I. Soclof

IPC: H01L21/265 ,  H01L21/762 ,  H01L21/8222 ,  H01L27/12 ,  H01L29/73

CPC classification number: H01L21/76237 ,  H01L21/26586 ,  H01L21/8222 ,  H01L29/7317 ,  H01L27/1203

Abstract: The invention provides a unique sub-micron dimensioned PNP-type transistor wherein hundreds of such transistors may be fabricated on a single chip with each transistor comprising an active region surrounded by field oxide completely isolating it from the substrate and its effects on operation. Slots made in the substrate permit angle evaporation of etch-resist to protect the active region while it is disconnected form the substrate by etching therebeneath via the slots. Substrate oxidation supports the active regions while orthogonal slots are provided permitting access to opposed sides of the active regions for doping N+ which is driven in from one side only while P or P+ is introduced and driven in from both sides, thereby providing a P+ N+N, P+ emitter, base, collector transistor active region to which electrical connections are applied using conventional techniques, providing almost complete reduction of the parasitic capacitances and resistances because of the total oxide isolation of the active regions from the substrate.

Abstract translation: 本发明提供了一种独特的亚微米尺寸的PNP型晶体管，其中可以在单个芯片上制造数百个这样的晶体管，其中每个晶体管包括由场氧化物包围的有源区域，其完全将其与衬底隔离，并且其对操作的影响。 在衬底中制成的槽允许蚀刻抗蚀剂的角度蒸发，以通过经由槽蚀刻而从衬底断开而保护有源区。 衬底氧化支持有源区，同时提供正交槽，允许进入有源区的相对侧用于掺杂N +，其仅在P或P +从两侧引入并驱动时从一侧驱动，从而提供P + N + N，P +发射极，基极，集电极晶体管有源区域，使用常规技术施加电连接，由于有源区域与基板的总氧化物隔离，几乎完全降低了寄生电容和电阻。

公开(公告)号：US4683399A

公开(公告)日：1987-07-28

申请号：US278528

申请日：1981-06-29

Applicant: Sidney I. Soclof

Inventor： Sidney I. Soclof

IPC: H01J40/02 ,  H01J1/308 ,  H01J1/34 ,  H01J47/00 ,  H01L29/90 ,  H01J40/16

CPC classification number: H01J1/308 ,  H01J1/34 ,  H01J2201/3423

Abstract: A vacuum electron device including a semiconductor device in a hermetically sealed container enclosing a vacuum. The device includes an electron emissive source for emitting electrons into the vacuum, and a collector for collecting electrons emitted from the electron emissive source and tranported through the vacuum. The device is subjected to a high internal electric field such that electrons in the emissive source are excited to energies greater than the electron affinity of the semiconductor body.

Abstract translation: 一种真空电子器件，其包括封闭真空的密封容器中的半导体器件。 该装置包括用于将电子发射到真空中的电子发射源，以及用于收集从电子发射源发射并传送通过真空的电子的收集器。 该器件受到高内部电场，使得发射源中的电子被激发到大于半导体本体的电子亲和力的能量。

公开(公告)号：US4522682A

公开(公告)日：1985-06-11

申请号：US390496

申请日：1982-06-21

Applicant: Sidney I. Soclof

Inventor： Sidney I. Soclof

IPC: H01L21/306 ,  H01L21/762 ,  H01L21/764 ,  B44C1/22 ,  C03C15/00 ,  H01L29/72

CPC classification number: H01L21/764 ,  H01L21/30608 ,  H01L21/76264 ,  H01L21/76289

Abstract: The invention provides a unique sub-micron dimensioned PNP type transistor and method of making the same, wherein hundreds of such transistors may be fabricated on a single chip with each transistor comprising an active region surrounded by field oxide completely isolating it from the substrate and its effects on operation. Spaced apart slots made in the substrate permit the introduction of orientation dependent etching fluid therein to at least substantially etch semi-arrays of active regions of the substrate away from the substrate except for spaced apart supports therealong. Oxidation serves to support the semi-arrays and subsequent steps directly from the substrate or by webs of oxidation along the tops of the semi-arrays connected to the substrate. The support is necessary while orthogonal slots are provided permitting access to opposed sides of the active regions for doping P+ from each end, which P+ is driven in from both sides to provide an P+NP+ emitter base collector transistor active region to which electrical connections are applied using conventional techniques providing almost complete reduction of the parasitic capacitances and resistances because of the total oxide isolation of the active regions from the substrate.

Abstract translation: 本发明提供了一种独特的亚微米尺寸的PNP型晶体管及其制造方法，其中可以在单个芯片上制造数百个这样的晶体管，每个晶体管包括由场氧化物包围的有源区域，其完全将其与衬底隔离， 对操作的影响。 在衬底中形成的间隔开的槽允许在其中引入取向相关的蚀刻流体，以至少基本上蚀刻基板的有源区的半阵列远离衬底，除了其间隔开的支撑。 氧化用于从衬底直接支撑半阵列和后续步骤，或者通过连接到衬底的半阵列顶部的氧化纤维网。 支撑是必需的，同时提供正交槽，允许进入有源区域的相对侧，用于从两端掺杂P +，P +从两侧驱动，以提供P + NP +发射极基极集电极晶体管有源区，电连接 使用常规技术施加，由于活性区域与基底的总氧化物隔离，几乎完全降低了寄生电容和电阻。

公开(公告)号：US4437226A

公开(公告)日：1984-03-20

申请号：US450309

申请日：1982-12-16

Applicant: Sidney I. Soclof

Inventor： Sidney I. Soclof

IPC: H01L21/265 ,  H01L21/306 ,  H01L21/331 ,  H01L21/762 ,  H01L29/735 ,  H01L21/31

CPC classification number: H01L29/6625 ,  H01L21/265 ,  H01L21/30608 ,  H01L21/76264 ,  H01L29/735 ,  H01L21/76281 ,  Y10S148/051 ,  Y10S148/085 ,  Y10S148/096 ,  Y10S148/143

Abstract: The invention provides a unique sub-micron dimensioned NPN type transistor and method of making the same wherein hundreds of such transistors may be fabricated on a single chip with each transistor comprising an active region surrounded by field oxide completely isolating it from the substrate and its effects on operation. Slots made in the substrate permit angle evaporation of etch-resist to protect the active region while it is disconnected from the substrate by etching therebeneath via the slots. Substrate oxidation supports the active regions while orthogonal slots are provided permitting access to opposed sides of the active regions for doping P+ which is driven in from one side only while N+ is introduced and driven in from both sides, thereby providing an N+, P+P, N+ emitter, base, collector transistor active region to which electrical connections are applied using conventional techniques, providing almost complete reduction of the parasitic capacitances and resistances because of the total oxide isolation of the active regions from the substrate.

Abstract translation: 本发明提供了一种独特的亚微米尺寸的NPN型晶体管及其制造方法，其中可以在单个芯片上制造数百个这样的晶体管，每个晶体管包括由场氧化物包围的有源区域，其完全将其与衬底隔离，并且其效应 操作。 在衬底中制成的槽允许蚀刻抗蚀剂的角度蒸发，以通过经由槽蚀刻而与衬底断开而保护有源区。 衬底氧化支持有源区，同时提供正交槽，允许进入有源区的相对侧用于掺杂P +，其仅在N +从两侧引入并驱动时从一侧被驱动，从而提供N +，P + P ，使用常规技术施加电连接的N +发射极，基极，集电极晶体管有源区，由于有源区与基底的总氧化物隔离，提供了寄生电容和电阻的几乎完全降低。

公开(公告)号：US4419150A

公开(公告)日：1983-12-06

申请号：US418862

申请日：1982-09-16

Applicant: Sidney I. Soclof

Inventor： Sidney I. Soclof

IPC: H01L21/263 ,  H01L21/762 ,  H01L29/10 ,  H01L29/735 ,  H01L21/22 ,  H01L21/265

CPC classification number: H01L29/735 ,  H01L21/2633 ,  H01L21/76237 ,  H01L29/1008

Abstract: The invention is a sub-micron dielectrically isolated transistor and method of making the same wherein hundreds of such transistors may be fabricated on a single chip with each transistor comprising an active region surrounded by a field oxide region, N+ spaced-apart doped portions within said regions and a P+ doped portion of said region spaced from each N+ doped portions, and electrical connections to the base P+ portion and the collector and emitter N+ portions. These regions are established by first forming boundary recesses about each active portion where a transistor will be formed, depositing arsenic in the recesses to form N+ regions in the transistor-active region adjacent the recesses, deepening the recesses, diffusing boron into the deepened recesses to dope the substrate P-type beneath the N+ regions and also between the N+ regions, and patterning and metallizing the substrate to develop the electrical connections of the base, emitter and collector electrodes.

Abstract translation: 本发明是一种亚微米介电隔离晶体管及其制造方法，其中可以在单个芯片上制造数百个这样的晶体管，每个晶体管包括由场氧化物区域包围的有源区域，所述有源区域在所述 区域和与每个N +掺杂部分间隔开的所述区域的P +掺杂部分，以及到基极P +部分和集电极和发射极N +部分的电连接。 这些区域通过首先在形成晶体管的每个有源部分上形成边界凹槽来建立，在凹槽中沉积砷以在与凹部相邻的晶体管有源区域中形成N +区域，使凹槽加深，将硼扩散到加深的凹槽中 将N +区域之下以及N +区域之间的衬底P型掺杂，并且对衬底进行图案化和金属化以显现基极，发射极和集电极的电连接。

公开(公告)号：US5043787A

公开(公告)日：1991-08-27

申请号：US66593

申请日：1987-06-24

Applicant: Sidney I. Soclof

Inventor： Sidney I. Soclof

IPC: H01L21/263 ,  H01L21/265 ,  H01L21/306 ,  H01L21/762 ,  H01L29/735

CPC classification number: H01L21/76237 ,  H01L21/2633 ,  H01L21/26586 ,  H01L21/30608 ,  H01L29/735

Abstract: An array of hundreds of devices may be simultaneously processed on a chip to sub-micron dimensions by establishing tiny active regions for each transistor surrounded by field oxide filled moats or slotted regions, wherein the slots are utilized to dope the substrate within the active region. The N type substrate is double energy boron planted through one surface to establish a P region to a given depth. This surface is oxidized and photoresist mask conventionally to open regions for the slots which are ion milled or ODE etched to a given depth. N+ regions are established by the slots by ion implanting at an angle such that the entire depth of the slot is not doped but rather the doping is confined to a region within the double energy P implanted depth. Drive-in diffusion enlarges the N+ areas for the emitter and collector and oxidation fills the moat insulating regions around the active area. The oxide is stripped and the P region enhanced to P+ at the surface, with silox being deposited and opened for metal contacts to the P+ region for the base and the emitter and collector region. The doping profile of the base region provides a potential barrier to minimize the flow of electrons toward the surface because the emitter electrons are channeled through the less heavily doped part of the base region to the collector.

Abstract translation: 通过为由场氧化物填充的沟槽或开槽区域围绕的每个晶体管建立微小的有源区，可以在芯片上将数百个器件的阵列同时处理为亚微米尺寸，其中所述槽用于在有源区域内掺杂衬底。 N型衬底是通过一个表面种植的双能硼，以建立到给定深度的P区。 该表面通常被氧化和光致抗蚀剂掩模打开用于被离子研磨的槽或ODE蚀刻到给定深度的区域。 通过离子注入以使角度的整个深度未掺杂的角度通过离子注入来建立N +区域，而是将掺杂限制在双能量P植入深度内的区域。 驱动扩散扩大了发射极和集电极的N +面积，氧化填充了有源区周围的护城河绝缘区域。 氧化物被剥离，并且P区在表面增强到P +，其中沉积并打开了用于金属接触到底层和发射极和集电极区域的P +区域的金属网。 基极区域的掺杂分布提供了一个势垒，以最小化电子朝向表面的流动，因为发射极电子通过基极区的较低掺杂部分被引导至集电极。

公开(公告)号：US4584762A

公开(公告)日：1986-04-29

申请号：US558073

申请日：1983-12-05

Applicant: Sidney I. Soclof

Inventor： Sidney I. Soclof

IPC: H01L21/265 ,  H01L21/762 ,  H01L29/10 ,  H01L29/735 ,  H01L21/302

CPC classification number: H01L21/265 ,  H01L21/76237 ,  H01L29/1008 ,  H01L29/735

Abstract: The invention is a transistor or array thereof and method for producing same in VLSI dimensions on a silicon substrate doped P or N type by forming intersecting slots in spaced apart relation across the substrate to define semiarrays of V shaped intermediate regions which will become transistors. Silicon oxide fills these slots and separates the transistor regions from the substrate. Orthogonal slots divided the semiarrays into individual transistor active regions which are doped by one of N or P doping introduced into each active regions via the orthogonal slots and driven in to comprise the emitter and collector regions on respective sides of original substrate comprising the base regions. Metallization patterns complete electrical connections to the emitter base and collector regions and silicon oxide substantially covers the periphery of each active region for total isolation. Each transistor may further comprise a doped region called P or N doping extending into and across the top of the base region underneath the metallization to reduce space region contact resistance and to provide an electron reflecting potential barrier. Each transistor may further comprise a doped skin of either P or N doping to force electrons toward the center of the base region.

Abstract translation: 本发明是一种晶体管或其阵列及其在掺杂P或N型硅衬底上的VLSI尺寸中的制造方法，其通过跨衬底形成间隔开的关系，形成将成为晶体管的V形中间区的半阵列。 硅氧化物填充这些槽并将晶体管区域与衬底分离。 正交时隙将半阵列分成单独的晶体管有源区，其通过经由正交狭缝引入到每个有源区中的N或P掺杂之一掺杂，并被驱动以在包含基极区的原始衬底的相应侧上包括发射极和集电极区。 金属化图案与发射极基极和集电极区域完全电连接，氧化硅基本上覆盖每个有源区域的周边以进行全部隔离。 每个晶体管还可以包括称为P或N掺杂的掺杂区域，其延伸到金属化之下的基极区域的顶部并跨过金属化层的顶部，以减少空间区域接触电阻并提供电子反射势垒。 每个晶体管还可以包括P或N掺杂的掺杂表皮，以迫使电子朝向基极区域的中心。

公开(公告)号：US4580331A

公开(公告)日：1986-04-08

申请号：US558072

申请日：1983-12-05

Applicant: Sidney I. Soclof

Inventor： Sidney I. Soclof

IPC: H01L21/265 ,  H01L21/762 ,  H01L21/8222 ,  H01L27/12 ,  H01L29/73 ,  H01L21/22 ,  H01L21/76

CPC classification number: H01L29/7317 ,  H01L21/265 ,  H01L21/76237 ,  H01L21/8222 ,  H01L27/1203

Abstract: The invention provides a unique VLSI dimensioned PNP-type transistor and method of making the same wherein hundreds of such transistors may be fabricated on a single chip with each transistor comprising an active region surrounded by field oxide completely isolating it from the substrate and its effects on operation. Slots made in the substrate permit angle evaporation of etch-resist to protect the active region while it is disconnected from the substrate by etching therebeneath via the slots. Substrate oxidation supports the active regions while orthogonal slots are provided permitting access to opposed sides of the active regions for doping N+ which is driven in from one side only while P or P+ is introduced and driven in from both sides, thereby providing a P+ N+N, P+ emitter, base, collector transistor active region to which electrical connections are applied using conventional techniques, providing almost complete reduction of the parasitic capacitances and resistances because of the total oxide isolation of the active regions from the substrate.

Abstract translation: 本发明提供了独特的VLSI尺寸尺寸的PNP型晶体管及其制造方法，其中可以在单个芯片上制造数百个这样的晶体管，每个晶体管包括由场氧化物包围的有源区域，其完全将其与衬底隔离，并且其对 操作。 在衬底中制成的槽允许蚀刻抗蚀剂的角度蒸发，以通过经由槽蚀刻而与衬底断开而保护有源区。 衬底氧化支持有源区，同时提供正交槽，允许进入有源区的相对侧用于掺杂N +，其仅在P或P +从两侧引入并驱动时从一侧驱动，从而提供P + N + N，P +发射极，基极，集电极晶体管有源区域，使用常规技术施加电连接，由于有源区域与基板的总氧化物隔离，几乎完全降低了寄生电容和电阻。