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    DATA CACHE CONTROLLER, DEVICES HAVING THE SAME, AND METHOD OF OPERATING THE SAME
    13.
    发明申请
    DATA CACHE CONTROLLER, DEVICES HAVING THE SAME, AND METHOD OF OPERATING THE SAME 有权
    数据缓存控制器，具有该数据缓存控制器的设备及其操作方法

    公开(公告)号：US20130117627A1

    公开(公告)日：2013-05-09

    申请号：US13446345

    申请日：2012-04-13

    Applicant: Sung Hyun Lee ,  Jun Hee Yoo

    Inventor： Sung Hyun Lee ,  Jun Hee Yoo

    IPC: G06F11/08 ,  G06F12/08

    CPC classification number: G06F12/0855 ,  G06F11/1064

    Abstract: An method of operating a data cache controller is provided. The method includes transmitting first data output from a data cache to a central processing unit (CPU) core with a first latency and transmitting second data to the CPU core with a second latency greater than the first latency. The first latency is a delay between a read request to the data cache and transmission of the first data according to execution of a first instruction fetched from an instruction cache, and the second latency is a delay between a read request to the data cache and transmission of the second data according to execution of a second instruction fetched from the instruction cache.

    Abstract translation: 提供了一种操作数据高速缓存控制器的方法。 该方法包括以第一等待时间将从数据高速缓存输出的第一数据传输到中央处理单元（CPU）核心，并以大于第一等待时间的第二等待时间向CPU核发送第二数据。 第一等待时间是根据从指令高速缓存取出的第一指令的执行，对数据高速缓存的读取请求和第一数据的传输之间的延迟，并且第二等待时间是对数据高速缓存和传输的读请求之间的延迟 根据从指令高速缓存取出的第二指令的执行来执行第二数据。

    Semiconductor memory device and internal data transmission method thereof
    14.
    发明授权
    Semiconductor memory device and internal data transmission method thereof 有权
    半导体存储器件及其内部数据传输方法

    公开(公告)号：US08050130B2

    公开(公告)日：2011-11-01

    申请号：US12798644

    申请日：2010-04-08

    Applicant: Sung-Hyun Lee ,  Dong-Soo Kang

    Inventor： Sung-Hyun Lee ,  Dong-Soo Kang

    IPC: G11C8/00

    CPC classification number: G11C7/1078 ,  G11C7/062 ,  G11C7/1015 ,  G11C7/109

    Abstract: In a semiconductor memory device and an internal data transmission method thereof, the device includes a memory controller, a pair of data lines, and a plurality of memory banks. During an internal data transmission operation, the memory controller externally receives and stores a source address and a target address in response to an externally applied command and outputs an internal control signal and an internal address signal using the source address and the target address. The internal control signal includes an internal write signal and an internal read signal. Transmission data is transmitted on the pair of data lines during the internal data transmission operation. The plurality of memory banks read the transmission data stored in a region corresponding to the source address in response to the internal read signal, transmit the transmission data on the pair of data lines, and write the transmission data transmitted on the pair of data lines in response to the internal write signal. During the internal data transmission operation, the transmission data is transmitted from the region corresponding to the source address to a region corresponding to the target address, and is not output external to the semiconductor memory device.

    Abstract translation: 在半导体存储器件及其内部数据传输方法中，该器件包括存储器控制器，一对数据线和多个存储器组。 在内部数据传输操作期间，存储器控制器响应于外部施加的命令从外部接收并存储源地址和目标地址，并使用源地址和目标地址输出内部控制信号和内部地址信号。 内部控制信号包括内部写入信号和内部读取信号。 在内部数据传输操作期间，在一对数据线上发送传输数据。 多个存储体响应于内部读取信号而读取存储在与源地址对应的区域中的发送数据，在该对数据线上发送发送数据，并将发送在该对数据线上的发送数据写入 响应内部写入信号。 在内部数据传输操作期间，将传输数据从与源地址相对应的区域发送到与目标地址相对应的区域，并且不在半导体存储器件外部输出。

    Data cache controller, devices having the same, and method of operating the same
    15.
    发明授权
    Data cache controller, devices having the same, and method of operating the same 有权
    数据缓存控制器，具有相同功能的设备及其操作方法

    公开(公告)号：US08645791B2

    公开(公告)日：2014-02-04

    申请号：US13446345

    申请日：2012-04-13

    Applicant: Sung Hyun Lee ,  Jun Hee Yoo

    Inventor： Sung Hyun Lee ,  Jun Hee Yoo

    IPC: H03M13/00 ,  G11C29/00

    CPC classification number: G06F12/0855 ,  G06F11/1064

    Abstract: An method of operating a data cache controller is provided. The method includes transmitting first data output from a data cache to a central processing unit (CPU) core with a first latency and transmitting second data to the CPU core with a second latency greater than the first latency. The first latency is a delay between a read request to the data cache and transmission of the first data according to execution of a first instruction fetched from an instruction cache, and the second latency is a delay between a read request to the data cache and transmission of the second data according to execution of a second instruction fetched from the instruction cache.

    Abstract translation: 提供了一种操作数据高速缓存控制器的方法。 该方法包括以第一等待时间将从数据高速缓存输出的第一数据传输到中央处理单元（CPU）核心，并以大于第一等待时间的第二等待时间向CPU核发送第二数据。 第一等待时间是根据从指令高速缓存取出的第一指令的执行，对数据高速缓存的读取请求和第一数据的传输之间的延迟，并且第二等待时间是对数据高速缓存和传输的读请求之间的延迟 根据从指令高速缓存取出的第二指令的执行来执行第二数据。

    MEMORY SYSTEM AND RELATED METHOD OF LOADING CODE
    16.
    发明申请
    MEMORY SYSTEM AND RELATED METHOD OF LOADING CODE 审中-公开
    存储器系统及相关加载代码的方法

    公开(公告)号：US20100318727A1

    公开(公告)日：2010-12-16

    申请号：US12780977

    申请日：2010-05-17

    Applicant: Sung Hyun LEE ,  Dongsoo KANG

    Inventor： Sung Hyun LEE ,  Dongsoo KANG

    IPC: G06F12/00 ,  G06F12/16

    CPC classification number: G06F12/0866 ,  G06F11/1446 ,  G06F2212/217

    Abstract: A memory system comprises a processor, a main memory comprising a volatile random access memory (RAM) that stores data to be accessed by the processor and a nonvolatile memory that provides a swap space for the RAM, and a disk that provides data transfer to the RAM with a greater latency than the nonvolatile memory.

    Abstract translation: 存储器系统包括处理器，主存储器，其包含存储由处理器访问的数据的易失性随机存取存储器（RAM）和为RAM提供交换空间的非易失性存储器，以及提供数据传送到 RAM具有比非易失性存储器更大的延迟。

    Optical power splitter having a stabilizing waveguide
    18.
    发明授权
    Optical power splitter having a stabilizing waveguide 失效
    具有稳定波导的光功率分配器

    公开(公告)号：US06961497B2

    公开(公告)日：2005-11-01

    申请号：US10303228

    申请日：2002-11-25

    Applicant: Heu-Gon Kim ,  Sung-Hyun Lee

    Inventor： Heu-Gon Kim ,  Sung-Hyun Lee

    IPC: G02B6/122 ,  G02B6/12 ,  G02B6/125 ,  G02B6/42

    CPC classification number: G02B6/125 ,  G02B2006/1215 ,  G02B2006/12195

    Abstract: An optical power splitter is provided that can stably operate even when there is a mode mismatch between an input optical signal and the optical power splitter. The optical power splitter of the present invention includes a semiconductor substrate, an optical waveguide stacked on the semiconductor substrate, and a clad surrounding the optical waveguide. The optical waveguide includes an input waveguide section through which the optical signal is input from an outer waveguide, a tapered waveguide section having a gradually increasing width, first and second waveguide branches extending from an output end of the tapered waveguide section and outputting first and second branched optical signals, and a stabilizing waveguide section disposed between the input waveguide section and the tapered waveguide section, the stabilizing waveguide section having length and width capable of stabilizing shaking of the optical signal which is generated by a mode mismatch between the optical signal and the input waveguide section.

    Abstract translation: 提供了一种即使在输入光信号和光功率分配器之间存在模式不匹配的情况下也能够稳定地操作的光功率分配器。 本发明的光功率分配器包括半导体衬底，堆叠在半导体衬底上的光波导和围绕光波导的包层。 光波导包括输入波导部分，光信号从外波导输入，逐渐增大的锥形波导部分，从锥形波导部分的输出端延伸的第一和第二波导分支，并输出第一和第二 分支光信号和设置在输入波导部分和锥形波导部分之间的稳定波导部分，稳定波导部分具有能够稳定由光信号和光信号之间的模式失配产生的光信号的抖动的长度和宽度 输入波导部分。

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