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    Bad page management in memory device or system
    4.
    发明授权
    Bad page management in memory device or system 有权
    内存设备或系统中的页面错误管理

    公开(公告)号：US08769356B2

    公开(公告)日：2014-07-01

    申请号：US13570568

    申请日：2012-08-09

    申请人： Hak-Soo Yu ,  Chul-Woo Park ,  Uk-Song Kang ,  Joo-Sun Choi ,  Hong-Sun Hwang ,  Jong-Pil Son

    发明人： Hak-Soo Yu ,  Chul-Woo Park ,  Uk-Song Kang ,  Joo-Sun Choi ,  Hong-Sun Hwang ,  Jong-Pil Son

    IPC分类号： G11C29/00 ,  G11C29/24

    CPC分类号： G11C29/24 ,  G11C29/00 ,  G11C29/76 ,  G11C29/785 ,  G11C2029/4402

    摘要： A memory device comprises a memory cell array and a bad page map. The memory cell array comprises a plurality of memory cells arranged in pages and columns, wherein the memory cell array is divided into a first memory block and a second memory block each corresponding to an array of the memory cells. The bad page map stores bad page location information indicating whether each of the pages of the first memory block is good or bad. A fail page address of the first memory block is replaced by a pass page address of the second memory block according to the bad page location information.

    摘要翻译： 存储器件包括存储单元阵列和坏页映射。 存储单元阵列包括以页和列排列的多个存储单元，其中存储单元阵列被划分为与存储单元阵列对应的第一存储块和第二存储块。 坏页面映射存储指示第一存储器块的每个页面是好是坏的页面位置信息。 根据坏页位置信息，第一存储块的失败页地址被第二存储块的通过页地址替换。

    Semiconductor devices having a three-dimensional stacked structure and methods of de-skewing data therein
    6.
    发明授权
    Semiconductor devices having a three-dimensional stacked structure and methods of de-skewing data therein 有权
    具有三维堆叠结构的半导体器件和其中的数据失真的方法

    公开(公告)号：US08488399B2

    公开(公告)日：2013-07-16

    申请号：US13108130

    申请日：2011-05-16

    申请人： Hak-Soo Yu ,  Sang-Bo Lee ,  Hong-Sun Hwang ,  Dong-Hyun Sohn

    发明人： Hak-Soo Yu ,  Sang-Bo Lee ,  Hong-Sun Hwang ,  Dong-Hyun Sohn

    IPC分类号： G11C7/00

    CPC分类号： G11C5/02 ,  G11C5/063 ,  G11C7/222 ,  G11C8/14 ,  G11C8/18 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/0061 ,  G11C29/02 ,  G11C29/025 ,  G11C29/028 ,  G11C29/50012 ,  G11C2213/71

    摘要： A semiconductor memory device having a 3D stacked structure includes: a first semiconductor area with a stacked structure of a first layer having first data and a second layer having second data; a first line for delivering an access signal for accessing the first semiconductor area; and a second line for outputting the first and/or second data from the first semiconductor area, wherein access timings of accessing the first and second layers are controlled so that a first time delay from the delivery of the access signal to the first layer to the output of the first data is substantially identical to a second time delay from the delivery of the access signal to the second layer to the output of the second data, thereby compensating for skew according to an inter-layer timing delay and thus performing a normal operation. Accordingly, the advantage of high-integration according to a stacked structure can be maximized by satisfying data input/output within a predetermined standard.

    摘要翻译： 具有3D堆叠结构的半导体存储器件包括：具有第一层的层叠结构的第一半导体区域和具有第二数据的第二层; 用于传送访问所述第一半导体区域的访问信号的第一行; 以及用于从第一半导体区域输出第一和/或第二数据的第二行，其中控制访问第一和第二层的访问定时，以便从接收信号传送到第一层到第一层的第一时间延迟 第一数据的输出与从接收信号传送到第二层到第二数据的输出的第二时间延迟基本相同，从而根据层间定时延迟补偿偏移，从而执行正常操作 。 因此，通过满足预定标准中的数据输入/输出，可以最大化根据堆叠结构的高集成度的优点。

    SEMICONDUCTOR MEMORY DEVICES AND SEMICONDUCTOR MEMORY SYSTEMS
    8.
    发明申请
    SEMICONDUCTOR MEMORY DEVICES AND SEMICONDUCTOR MEMORY SYSTEMS 有权
    半导体存储器件和半导体存储器系统

    公开(公告)号：US20120106281A1

    公开(公告)日：2012-05-03

    申请号：US13282830

    申请日：2011-10-27

    申请人： Sua KIM ,  Chul-woo PARK ,  Hong-sun HWANG ,  Hak-soo YU

    发明人： Sua KIM ,  Chul-woo PARK ,  Hong-sun HWANG ,  Hak-soo YU

    IPC分类号： G11C7/06 ,  G11C8/08 ,  G11C8/10 ,  G11C7/12

    CPC分类号： G11C7/18 ,  G11C7/06 ,  G11C2207/002 ,  G11C2207/005

    摘要： A semiconductor memory device includes at least one memory cell block and at least one connection unit. The at least one memory cell block has a first region including at least one first memory cell connected to a first bit line, and a second region including at least one second memory cell connected to a second bit line. The at least one connection unit is configured to selectively connect the first bit line to a corresponding bit line sense amplifier based on a first control signal, and configured to selectively connect the second bit line to the corresponding bit line sense amplifier via a corresponding global bit line based on a second control signal.

    摘要翻译： 半导体存储器件包括至少一个存储单元块和至少一个连接单元。 所述至少一个存储单元块具有包括连接到第一位线的至少一个第一存储单元的第一区域和包括连接到第二位线的至少一个第二存储器单元的第二区域。 所述至少一个连接单元被配置为基于第一控制信号选择性地将第一位线连接到对应的位线读出放大器，并且被配置为经由对应的全局位选择性地将第二位线连接到对应的位线读出放大器 基于第二控制信号。

    SEMICONDUCTOR MEMORY DEVICE HAVING STACKED STRUCTURE INCLUDING RESISTOR-SWITCHED BASED LOGIC CIRCUIT AND METHOD OF MANUFACTURING THE SAME
    9.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE HAVING STACKED STRUCTURE INCLUDING RESISTOR-SWITCHED BASED LOGIC CIRCUIT AND METHOD OF MANUFACTURING THE SAME 有权
    具有堆叠结构的半导体存储器件，包括基于电阻开关的逻辑电路及其制造方法

    公开(公告)号：US20120063194A1

    公开(公告)日：2012-03-15

    申请号：US13224410

    申请日：2011-09-02

    申请人： In-gyu BAEK ,  Hong-sun HWANG ,  Hak-soo YU ,  Chul-woo PARK

    发明人： In-gyu BAEK ,  Hong-sun HWANG ,  Hak-soo YU ,  Chul-woo PARK

    IPC分类号： G11C11/00 ,  H01L45/00

    CPC分类号： H01L45/147 ,  G11C5/025 ,  G11C13/0002 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/14

    摘要： Semiconductor memory device having a stacking structure including resistor switch based logic circuits. The semiconductor memory device includes a first conductive line that includes a first line portion and a second line portion, wherein the first line portion and the second line portion are electrically separated from each other by an intermediate region disposed between the first and second line portions, a first variable resistance material film that is connected to the first line portion and stores data, and a second variable resistance material film that controls an electrical connection between the first line portion and the second line portion.

    摘要翻译： 具有包括基于电阻器开关的逻辑电路的堆叠结构的半导体存储器件。 半导体存储器件包括第一导线，其包括第一线部分和第二线部分，其中第一线部分和第二线部分通过布置在第一线部分和第二线部分之间的中间区域彼此电分离， 连接到第一线部分并存储数据的第一可变电阻材料膜和控制第一线部分和第二线部分之间的电连接的第二可变电阻材料膜。

    Semiconductor Devices Having a Three-Dimensional Stacked Structure and Methods of De-Skewing Data Therein
    10.
    发明申请
    Semiconductor Devices Having a Three-Dimensional Stacked Structure and Methods of De-Skewing Data Therein 有权
    具有三维堆叠结构的半导体器件及其中的数据偏移方法

    公开(公告)号：US20110286254A1

    公开(公告)日：2011-11-24

    申请号：US13108130

    申请日：2011-05-16

    申请人： Hak-Soo Yu ,  Sang-Bo Lee ,  Hong-Sun Hwang ,  Dong-Hyun Sohn

    发明人： Hak-Soo Yu ,  Sang-Bo Lee ,  Hong-Sun Hwang ,  Dong-Hyun Sohn

    IPC分类号： G11C5/02

    CPC分类号： G11C5/02 ,  G11C5/063 ,  G11C7/222 ,  G11C8/14 ,  G11C8/18 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/0061 ,  G11C29/02 ,  G11C29/025 ,  G11C29/028 ,  G11C29/50012 ,  G11C2213/71

    摘要： A semiconductor memory device having a 3D stacked structure includes: a first semiconductor area with a stacked structure of a first layer having first data and a second layer having second data; a first line for delivering an access signal for accessing the first semiconductor area; and a second line for outputting the first and/or second data from the first semiconductor area, wherein access timings of accessing the first and second layers are controlled so that a first time delay from the delivery of the access signal to the first layer to the output of the first data is substantially identical to a second time delay from the delivery of the access signal to the second layer to the output of the second data, thereby compensating for skew according to an inter-layer timing delay and thus performing a normal operation. Accordingly, the advantage of high-integration according to a stacked structure can be maximized by satisfying data input/output within a predetermined standard.

    摘要翻译： 具有3D堆叠结构的半导体存储器件包括：具有第一层的层叠结构的第一半导体区域和具有第二数据的第二层; 用于传送访问所述第一半导体区域的访问信号的第一行; 以及用于从第一半导体区域输出第一和/或第二数据的第二行，其中控制访问第一和第二层的访问定时，以便从接收信号传送到第一层到第一层的第一时间延迟 第一数据的输出与从接收信号传送到第二层到第二数据的输出的第二时间延迟基本相同，从而根据层间定时延迟补偿偏移，从而执行正常操作 。 因此，通过满足预定标准中的数据输入/输出，可以最大化根据堆叠结构的高集成度的优点。