公开(公告)号：US07884393B2

公开(公告)日：2011-02-08

申请号：US12786440

申请日：2010-05-25

Applicant: Shin Hashimoto ,  Makoto Kiyama ,  Takashi Sakurada ,  Tatsuya Tanabe ,  Kouhei Miura ,  Tomihito Miyazaki

Inventor： Shin Hashimoto ,  Makoto Kiyama ,  Takashi Sakurada ,  Tatsuya Tanabe ,  Kouhei Miura ,  Tomihito Miyazaki

IPC: H01L29/778

CPC classification number: H01L29/7787 ,  H01L21/02389 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02573 ,  H01L21/0262 ,  H01L29/2003 ,  H01L29/66462

Abstract: Affords high electron mobility transistors having a high-purity channel layer and a high-resistance buffer layer. A high electron mobility transistor (11) is provided with a supporting substrate (13) composed of gallium nitride, a buffer layer (15) composed of a first gallium nitride semiconductor, a channel layer (17) composed of a second gallium nitride semiconductor, a semiconductor layer (19) composed of a third gallium nitride semiconductor, and electrode structures (a gate electrode (21), a source electrode (23) and a drain electrode (25) for the transistor (11). The band gap of the third gallium nitride semiconductor is broader than that of the second gallium nitride semiconductor. The carbon concentration NC1 of the first gallium nitride semiconductor is 4×1017 cm−3 or more. The carbon concentration NC2 of the second gallium nitride semiconductor is less than 4×1016 cm−3.

Abstract translation: 提供具有高纯度沟道层和高电阻缓冲层的高电子迁移率晶体管。 高电子迁移率晶体管（11）设置有由氮化镓构成的支撑基板（13），由第一氮化镓半导体构成的缓冲层（15），由第二氮化镓半导体构成的沟道层（17） 由第三氮化镓半导体构成的半导体层（19）和用于晶体管（11）的电极结构（栅电极（21），源电极（23）和漏电极（25）），带隙 第三氮化镓半导体的第二氮化镓半导体的碳浓度NC2比第二氮化镓半导体的碳浓度小于4×10 17 cm -3以上， 1016厘米-3。

公开(公告)号：US07749828B2

公开(公告)日：2010-07-06

申请号：US11571156

申请日：2006-03-03

Applicant: Shin Hashimoto ,  Makoto Kiyama ,  Takashi Sakurada ,  Tatsuya Tanabe ,  Kouhei Miura ,  Tomihito Miyazaki

Inventor： Shin Hashimoto ,  Makoto Kiyama ,  Takashi Sakurada ,  Tatsuya Tanabe ,  Kouhei Miura ,  Tomihito Miyazaki

IPC: H01L21/338

CPC classification number: H01L29/7787 ,  H01L21/02389 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02573 ,  H01L21/0262 ,  H01L29/2003 ,  H01L29/66462

Abstract: Affords high electron mobility transistors having a high-purity channel layer and a high-resistance buffer layer. A high electron mobility transistor 11 is provided with a supporting substrate 13 composed of gallium nitride, a buffer layer 15 composed of a first gallium nitride semiconductor, a channel layer 17 composed of a second gallium nitride semiconductor, a semiconductor layer 19 composed of a third gallium nitride semiconductor, and electrode structures (a gate electrode 21, a source electrode 23 and a drain electrode 25) for the transistor 11. The band gap of the third gallium nitride semiconductor is broader than that of the second gallium nitride semiconductor. The carbon concentration NC1 of the first gallium nitride semiconductor is 4×1017 cm−3 or more. The carbon concentration NC2 of the second gallium nitride semiconductor is less than 4×1016 cm−3.

Abstract translation: 提供具有高纯度沟道层和高电阻缓冲层的高电子迁移率晶体管。 高电子迁移率晶体管11设置有由氮化镓构成的支撑基板13，由第一氮化镓半导体构成的缓冲层15，由第二氮化镓半导体构成的沟道层17，由第三氮化镓半导体构成的半导体层19 氮化镓半导体，以及用于晶体管11的电极结构（栅电极21，源电极23和漏电极25）。第三氮化镓半导体的带隙比第二氮化镓半导体的带隙宽。 第一氮化镓半导体的碳浓度NC1为4×1017cm-3以上。 第二氮化镓半导体的碳浓度NC2小于4×1016cm-3。

公开(公告)号：US08410524B2

公开(公告)日：2013-04-02

申请号：US11569500

申请日：2006-03-06

Applicant: Tatsuya Tanabe ,  Kouhei Miura ,  Makoto Kiyama ,  Takashi Sakurada

Inventor： Tatsuya Tanabe ,  Kouhei Miura ,  Makoto Kiyama ,  Takashi Sakurada

IPC: H01L29/66

CPC classification number: H01L29/7787 ,  H01L21/02389 ,  H01L21/02458 ,  H01L21/0254 ,  H01L29/2003

Abstract: Affords Group III nitride semiconductor devices in which the leakage current from the Schottky electrode can be reduced. In a high electron mobility transistor 11, a supporting substrate 13 is composed of AlN, AlGaN, or GaN, specifically. An AlYGa1−YN epitaxial layer 15 has a full-width-at-half maximum of (0002) plane XRD of 150 sec or less. A GaN epitaxial layer 17 is provided between the gallium nitride supporting substrate and the AlYGa1−YN epitaxial layer (0

Abstract translation: 提供可以减少来自肖特基电极的漏电流的III族氮化物半导体器件。 在高电子迁移率晶体管11中，支撑衬底13具体地由AlN，AlGaN或GaN构成。 AlYGa1-YN外延层15具有150秒或更小的（0002）面XRD的全宽度的最大值。 在氮化镓支撑衬底和AlYGa1-YN外延层（0

公开(公告)号：US08148751B2

公开(公告)日：2012-04-03

申请号：US12732775

申请日：2010-03-26

Applicant: Shin Hashimoto ,  Tatsuya Tanabe ,  Katsushi Akita ,  Hideaki Nakahata ,  Hiroshi Amano

Inventor： Shin Hashimoto ,  Tatsuya Tanabe ,  Katsushi Akita ,  Hideaki Nakahata ,  Hiroshi Amano

IPC: H01L29/66

CPC classification number: H01L29/7787 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02609 ,  H01L21/0262 ,  H01L21/02661 ,  H01L29/2003 ,  H01L29/66212 ,  H01L29/66462 ,  H01L29/872

Abstract: A group III nitride semiconductor device and a group III nitride semiconductor wafer are provided. The group III nitride semiconductor device has a channel layer comprising group III nitride-based semiconductor containing Al. The group III nitride semiconductor device can enhance the mobility of the two-dimensional electron gas and improve current characteristics. The group III nitride semiconductor wafer is used to make the group III nitride semiconductor device. The group III nitride semiconductor wafer comprises a substrate made of AlXGa1-XN (0

Abstract translation: 提供III族氮化物半导体器件和III族氮化物半导体晶片。 III族氮化物半导体器件具有包含含有Al的III族氮化物基半导体的沟道层。 III族氮化物半导体器件可以增强二维电子气的迁移率并改善电流特性。 III族氮化物半导体晶片用于制造III族氮化物半导体器件。 III族氮化物半导体晶片包括由Al x Ga 1-x N（0

公开(公告)号：US20120006263A1

公开(公告)日：2012-01-12

申请号：US12999973

申请日：2009-08-06

Applicant: Shin Hashimoto ,  Tatsuya Tanabe

Inventor： Shin Hashimoto ,  Tatsuya Tanabe

IPC: B05C9/14 ,  H01L21/00 ,  C23C16/34 ,  B05C11/00 ,  C23C16/46

CPC classification number: C23C16/46 ,  C30B25/10 ,  C30B25/16 ,  H01L21/02381 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/02502 ,  H01L21/02507 ,  H01L21/0254 ,  H01L21/0262

Abstract: When a film is to be deposited on a semiconductor substrate or the like in a heating ambient, the semiconductor substrate is caused to warp (curve) to a considerable extent merely due to an increased temperature. The warpage leads to problems such as degradation of the homogeneity of the quality of the film deposited on the substrate and a high possibility of generation of a crack in the substrate. Accordingly, a film deposition apparatus of the present invention heats the substrate both from above and from below a main surface of the substrate so that a temperature gradient (temperature difference) between the upper side and the lower side of the main surface is reduced and the warpage of the substrate is suppressed. More preferably a measurement unit for measuring the curvature or warpage of the substrate is included.

Abstract translation: 当在加热环境中将膜沉积在半导体衬底等上时，仅仅由于温度升高，使半导体衬底在很大程度上翘曲（曲线）。 翘曲导致诸如沉积在基底上的膜的质量均匀性降低和在基底中产生裂纹的可能性高的问题。 因此，本发明的成膜装置从基板的主面的上方和下方加热基板，使得主表面的上侧和下侧之间的温度梯度（温度差）减小，并且 抑制了基板的翘曲。 更优选地包括用于测量基板的曲率或翘曲的测量单元。

公开(公告)号：US20110049573A1

公开(公告)日：2011-03-03

申请号：US12732775

申请日：2010-03-26

Applicant: Shin HASHIMOTO ,  Tatsuya TANABE ,  Katsushi AKITA ,  Hideaki NAKAHATA ,  Hiroshi AMANO

Inventor： Shin HASHIMOTO ,  Tatsuya TANABE ,  Katsushi AKITA ,  Hideaki NAKAHATA ,  Hiroshi AMANO

IPC: H01L29/205

CPC classification number: H01L29/7787 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02609 ,  H01L21/0262 ,  H01L21/02661 ,  H01L29/2003 ,  H01L29/66212 ,  H01L29/66462 ,  H01L29/872

Abstract: A group III nitride semiconductor device and a group III nitride semiconductor wafer are provided. The group III nitride semiconductor device has a channel layer comprising group III nitride-based semiconductor containing Al. The group III nitride semiconductor device can enhance the mobility of the two-dimensional electron gas and improve current characteristics. The group III nitride semiconductor wafer is used to make the group III nitride semiconductor device. The group III nitride semiconductor wafer comprises a substrate made of AlXGa1−XN (0

Abstract translation: 提供III族氮化物半导体器件和III族氮化物半导体晶片。 III族氮化物半导体器件具有包含含有Al的III族氮化物基半导体的沟道层。 III族氮化物半导体器件可以增强二维电子气的迁移率并改善电流特性。 III族氮化物半导体晶片用于制造III族氮化物半导体器件。 III族氮化物半导体晶片包括由Al x Ga 1-x N（0

公开(公告)号：US07872285B2

公开(公告)日：2011-01-18

申请号：US11569798

申请日：2006-03-01

Applicant: Shin Hashimoto ,  Makoto Kiyama ,  Tatsuya Tanabe ,  Kouhei Miura ,  Takashi Sakurada

Inventor： Shin Hashimoto ,  Makoto Kiyama ,  Tatsuya Tanabe ,  Kouhei Miura ,  Takashi Sakurada

IPC: H01L29/66 ,  H01L29/207 ,  H01L29/20

CPC classification number: H01L29/7802 ,  H01L29/0878 ,  H01L29/2003 ,  H01L29/8611 ,  H01L29/872

Abstract: Affords epitaxial substrates for vertical gallium nitride semiconductor devices that have a structure in which a gallium nitride film of n-type having a desired low carrier concentration can be provided on a gallium nitride substrate of n type. A gallium nitride epitaxial film (65) is provided on a gallium nitride substrate (63). A layer region (67) is provided in the gallium nitride substrate (63) and the gallium nitride epitaxial film (65). An interface between the gallium nitride substrate (43) and the gallium nitride epitaxial film (65) is positioned in the layer region (67). In the layer region (67), a peak value of donor impurity along an axis from the gallium nitride substrate (63) to the gallium nitride epitaxial film (65) is 1×1018 cm−3 or more. The donor impurity is at least either silicon or germanium.

Abstract translation: 提供具有这样的结构的垂直氮化镓半导体器件的外延衬底，其中可以在n型氮化镓衬底上提供具有期望的低载流子浓度的n型氮化镓膜。 氮化镓外延膜（65）设置在氮化镓衬底（63）上。 在氮化镓衬底（63）和氮化镓外延膜（65）中设置一个层区（67）。 氮化镓衬底（43）和氮化镓外延膜（65）之间的界面位于层区（67）中。 在层区域（67）中，供体杂质从氮化镓衬底（63）到氮化镓外延膜（65）的峰的峰值为1×1018cm-3以上。 供体杂质至少是硅或锗。

公开(公告)号：US20100230723A1

公开(公告)日：2010-09-16

申请号：US12786440

申请日：2010-05-25

Applicant: Shin Hashimoto ,  Makoto Kiyama ,  Takashi Sakurada ,  Tatsuya Tanabe ,  Kouhei Miura ,  Tomihito Miyazaki

Inventor： Shin Hashimoto ,  Makoto Kiyama ,  Takashi Sakurada ,  Tatsuya Tanabe ,  Kouhei Miura ,  Tomihito Miyazaki

IPC: H01L29/778 ,  H01L29/12

CPC classification number: H01L29/7787 ,  H01L21/02389 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02573 ,  H01L21/0262 ,  H01L29/2003 ,  H01L29/66462

Abstract: Affords high electron mobility transistors having a high-purity channel layer and a high-resistance buffer layer. A high electron mobility transistor (11) is provided with a supporting substrate (13) composed of gallium nitride, a buffer layer (15) composed of a first gallium nitride semiconductor, a channel layer (17) composed of a second gallium nitride semiconductor, a semiconductor layer (19) composed of a third gallium nitride semiconductor, and electrode structures (a gate electrode (21), a source electrode (23) and a drain electrode (25)) for the transistor (11). The band gap of the third gallium nitride semiconductor is broader than that of the second gallium nitride semiconductor. The carbon concentration NC1 of the first gallium nitride semiconductor is 4×1017 cm−3 or more. The carbon concentration NC2 of the second gallium nitride semiconductor is less than 4×1016 cm−3.

Abstract translation: 提供具有高纯度沟道层和高电阻缓冲层的高电子迁移率晶体管。 高电子迁移率晶体管（11）设置有由氮化镓构成的支撑衬底（13），由第一氮化镓半导体构成的缓冲层（15），由第二氮化镓半导体构成的沟道层（17） 由第三氮化镓半导体构成的半导体层（19）和用于晶体管（11）的电极结构（栅电极（21），源电极（23）和漏电极（25））。 第三氮化镓半导体的带隙比第二氮化镓半导体的带隙宽。 第一氮化镓半导体的碳浓度NC1为4×1017cm-3以上。 第二氮化镓半导体的碳浓度NC2小于4×1016cm-3。

公开(公告)号：US08404571B2

公开(公告)日：2013-03-26

申请号：US13000835

申请日：2009-06-25

Applicant: Shin Hashimoto ,  Tatsuya Tanabe

Inventor： Shin Hashimoto ,  Tatsuya Tanabe

IPC: H01L21/02 ,  C23C16/30 ,  C30B25/02 ,  C30B29/40

CPC classification number: C23C16/303 ,  C30B25/02 ,  C30B29/403 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02658

Abstract: Provided is a film deposition method capable of improving the crystal characteristic near an interface according to the lattice constant of a material that will constitute a thin film to be deposited. Specifically, a substrate is curved relative to the direction along one main surface on which the thin film is to be deposited, according to the lattice constant the material that will constitute the thin film to be deposited and the lattice constant of a material constituting the one main surface. The thin film is deposited on the one main surface of the substrate with the substrate curved.

Abstract translation: 提供一种能够根据构成要沉积的薄膜的材料的晶格常数来改善界面附近的晶体特性的成膜方法。 具体地，基板相对于沿着要沉积薄膜的一个主表面的方向弯曲，根据构成要沉积的薄膜的材料的晶格常数和构成该薄膜的材料的晶格常数 主表面。 薄膜沉积在基板的一个主表面上，基板弯曲。

公开(公告)号：US20110097880A1

公开(公告)日：2011-04-28

申请号：US13000835

申请日：2009-06-25

Applicant: Shin Hashimoto ,  Tatsuya Tanabe

Inventor： Shin Hashimoto ,  Tatsuya Tanabe

IPC: H01L21/20

CPC classification number: C23C16/303 ,  C30B25/02 ,  C30B29/403 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02658

Abstract: Provided is a film deposition method capable of improving the crystal characteristic near an interface according to the lattice constant of a material that will constitute a thin film to be deposited. Specifically, a substrate is curved relative to the direction along one main surface on which the thin film is to be deposited, according to the lattice constant the material that will constitute the thin film to be deposited and the lattice constant of a material constituting the one main surface. The thin film is deposited on the one main surface of the substrate with the substrate curved.

Abstract translation: 提供一种能够根据构成要沉积的薄膜的材料的晶格常数来改善界面附近的晶体特性的成膜方法。 具体地，基板相对于沿着要沉积薄膜的一个主表面的方向弯曲，根据构成要沉积的薄膜的材料的晶格常数和构成该薄膜的材料的晶格常数 主表面。 薄膜沉积在基板的一个主表面上，基板弯曲。