公开(公告)号：US20240355620A1

公开(公告)日：2024-10-24

申请号：US18713455

申请日：2022-10-25

Applicant: SHIN-ETSU HANDOTAI CO., LTD

Inventor： Ippei KUBONO ,  Keitaro TSUCHIYA ,  Kazunori HAGIMOTO ,  Keisuke MIHARA ,  Kosei SUGAWARA

IPC: H01L21/02 ,  H01L29/20 ,  H01L29/786

CPC classification number: H01L21/02389 ,  H01L21/0242 ,  H01L21/0262 ,  H01L29/2003 ,  H01L29/7869

Abstract: A nitride semiconductor substrate includes: a silicon single-crystal substrate; and a nitride semiconductor thin film formed on the silicon single-crystal substrate, wherein the silicon single-crystal substrate has a carbon concentration of 5E16 atoms/cm3 or more and 2E17 atoms/cm3 or less. This provides a nitride semiconductor substrate resistant against plastic deformation and a manufacturing method therefor.

公开(公告)号：US12116697B2

公开(公告)日：2024-10-15

申请号：US17773475

申请日：2020-12-24

Applicant: TOKUYAMA CORPORATION

Inventor： Toru Nagashima

IPC: C30B29/40 ,  C30B25/20 ,  C30B33/00 ,  H01L21/02

CPC classification number: C30B29/403 ,  C30B25/20 ,  C30B33/00 ,  H01L21/02024 ,  H01L21/02389 ,  H01L21/0254

Abstract: A group III nitride single crystal substrate comprises: a first main face; and a first back face opposite to the first main face, wherein an absolute value of a radius of curvature of the first main face of the substrate is 10 m or more; an absolute value of a radius of curvature of a crystal lattice plane at a center of the first main face of the substrate is 10 m or more; and a 1/1000 intensity width of an X-ray rocking curve of a low-incidence-angle face at the center of the first main face of the substrate is 1200 arcsec or less.

公开(公告)号：US20240339320A1

公开(公告)日：2024-10-10

申请号：US18297462

申请日：2023-04-07

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chi-Ming CHEN ,  Chia-Shiung TSAI ,  Chung-Yuan LI

IPC: H01L21/02 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L21/02617 ,  H01L21/02389 ,  H01L21/0245 ,  H01L21/02502 ,  H01L21/02516 ,  H01L21/0254 ,  H01L29/66462 ,  H01L29/7786 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02458 ,  H01L21/02513 ,  H01L21/02658 ,  H01L21/31111 ,  H01L21/32055 ,  H01L21/32134 ,  H01L29/2003

Abstract: Using surface activated bonding (SAB) allows direct bonding of a silicon growth seed layer over an aluminum nitride substrate without an intervening oxide layer. The growth seed layer may include p− Si(111) in order to allow for epitaxy of gallium nitride without exacerbating CTE mismatch between silicon and the gallium nitride. As a result, defects in the gallium nitride are reduced, and bowing and cracking of the substrate is reduced, which improves performance of an electronic device including the gallium nitride. Additionally, using SAB is faster than other techniques for forming a growth seed layer as well as conserving power, processing resources, and raw materials that otherwise would have been expended in forming the growth seed layer.

公开(公告)号：US12107126B2

公开(公告)日：2024-10-01

申请号：US17747947

申请日：2022-05-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Peter Ramvall ,  Matthias Passlack

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/12 ,  H01L29/15 ,  H01L29/20 ,  H01L29/78

CPC classification number: H01L29/122 ,  H01L21/02389 ,  H01L29/152 ,  H01L29/2003 ,  H01L29/66666 ,  H01L29/7827

Abstract: The current disclosure describes a vertical tunnel FET device including a vertical P-I-N heterojunction structure of a P-doped nanowire gallium nitride source/drain, an intrinsic InN layer, and an N-doped nanowire gallium nitride source/drain. A high-K dielectric layer and a metal gate wrap around the intrinsic InN layer.

公开(公告)号：US12100936B2

公开(公告)日：2024-09-24

申请号：US17767293

申请日：2020-10-08

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Toshiyuki Takizawa

IPC: H01L33/00 ,  H01L21/02 ,  H01L33/18 ,  H01S5/327

CPC classification number: H01S5/327 ,  H01L21/02381 ,  H01L21/02389 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/02494 ,  H01L21/02516 ,  H01L21/02521 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/02609 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02647 ,  H01L21/0265 ,  H01L33/002 ,  H01L33/005 ,  H01L33/18 ,  H01L21/02488 ,  H01L21/02502

Abstract: A nitride semiconductor structure includes a Group III nitride semiconductor portion and a Group II-IV nitride semiconductor portion. The Group III nitride semiconductor portion is single crystalline. The Group III nitride semiconductor portion has a predetermined crystallographic plane. The Group II-IV nitride semiconductor portion is provided on the predetermined crystallographic plane of the Group III nitride semiconductor portion. The Group II-IV nitride semiconductor portion is single crystalline. The Group II-IV nitride semiconductor portion contains a Group II element and a Group IV element. The Group II-IV nitride semiconductor portion forms a heterojunction with the Group III nitride semiconductor portion. The predetermined crystallographic plane is a crystallographic plane other than a (0001) plane.

公开(公告)号：US20240304675A1

公开(公告)日：2024-09-12

申请号：US18595013

申请日：2024-03-04

Applicant: ENKRIS SEMICONDUCTOR, INC.

Inventor： Kai CHENG

IPC: H01L29/20 ,  H01L21/02 ,  H01L21/265

CPC classification number: H01L29/2003 ,  H01L21/02389 ,  H01L21/2654

Abstract: Disclosed are a composite substrate, a semiconductor structure, and a manufacturing method for a composite substrate. The composite substrate includes single-crystal AlN; a support substrate disposed below a bottom of the single-crystal AlN; and a transition layer disposed between the single-crystal AlN and the support substrate, where the transition layer includes an oxygen element. In the composite substrate provided by the present disclosure, mechanical strength of the single-crystal AlN may be indirectly improved through a supporting effect performed on the single-crystal AlN by the support substrate located below the bottom of the single-crystal AlN. Meanwhile, the support substrate also plays a role in regulating the stress on the single-crystal AlN, thereby reducing a warping degree of the single-crystal AlN during the subsequent epitaxial process and avoiding the occurrence of cracks or fragments.

公开(公告)号：US20240274545A1

公开(公告)日：2024-08-15

申请号：US18602684

申请日：2024-03-12

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Clifford Drowley ,  Ray Milano ,  Robert Routh ,  Subhash Srinivas Pidaparthi ,  Andrew P. Edwards

IPC: H01L23/544 ,  H01L21/02 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L23/544 ,  H01L21/02389 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/66795 ,  H01L29/785 ,  H01L2223/54426

Abstract: A method of forming alignment marks includes providing a III-V compound substrate having a device region and an alignment mark region, forming a hardmask layer having a first set of openings on the alignment mark region exposing a first surface portion of the III-V compound substrate and a second set of openings on the device region exposing a second surface portion of the III-V compound substrate, etching the exposed surface of the III-V compound substrate using the hardmask layer as a mask to form a plurality of trenches, and epitaxially regrowing a semiconductor layer in the trenches to form the alignment marks extending to a predetermined height over the processing surface of the III-V compound substrate.

公开(公告)号：US20240153763A1

公开(公告)日：2024-05-09

申请号：US18486471

申请日：2023-10-13

Applicant: Massachusetts Institute of Technology ,  The Government of the United States of America, as Represented by the Secretary of the Navy ,  ROHM Co. Ltd.

Inventor： Rachael L. Myers-Ward ,  Jeehwan Kim ,  Kuan Qiao ,  Wei Kong ,  David Kurt Gaskill ,  Takuji Maekawa ,  Noriyuki Masago

IPC: H01L21/02

CPC classification number: H01L21/02529 ,  H01L21/02378 ,  H01L21/02389 ,  H01L21/02433 ,  H01L21/02444 ,  H01L21/02458 ,  H01L21/02502 ,  H01L21/02598 ,  H01L21/0262

Abstract: Systems and methods for growth of silicon carbide over a layer comprising graphene and/or hexagonal boron nitride, and related articles, are generally described. In some embodiments, a SiC film is fabricated over a layer comprising graphene and/or hexagonal boron nitride, which in turn is disposed over a substrate. The layer and/or the substrate may be lattice-matched with the SiC film to reduce defect density in the SiC film. The fabricated SiC film may then be removed from the substrate via, for example, a stressor attached to the SiC film. In certain cases, the layer serves as a reusable platform for growing SiC films and also serves a release layer that allows fast, precise, and repeatable release at the layer surface.

公开(公告)号：US11967617B2

公开(公告)日：2024-04-23

申请号：US16759004

申请日：2018-08-08

Applicant: SUMITOMO CHEMICAL COMPANY, LIMITED

Inventor： Fumimasa Horikiri ,  Takehiro Yoshida

IPC: C30B29/38 ,  C23C16/34 ,  C30B25/18 ,  C30B29/40 ,  H01L21/02 ,  H01L29/20

CPC classification number: H01L29/2003 ,  C23C16/34 ,  C30B25/18 ,  C30B29/38 ,  C30B29/40 ,  H01L21/02293 ,  H01L21/02389 ,  H01L21/02433

Abstract: A nitride semiconductor substrate including a group III nitride semiconductor crystal and having a main surface, wherein a low index crystal plane is (0001) plane curved in a concave spherical shape to the main surface, and the off-angle (θm, θa) at a position (x, y) in the main surface approximated by x representing a coordinate in a direction along axis, y is a coordinate in a direction along axis, (0, 0) represents a coordinate (x, y) of the center, θm represents a direction component along axis in an off-angle of axis with respect to a normal, θa represents a direction component along axis in the off-angle, (M1, A1) represents a rate of change in the off-angle (θm, θa) with respect to the position (x, y) in the main surface, and (M2, A2) represents the off-angle (θm, θa) at the center.

公开(公告)号：US11949212B2

公开(公告)日：2024-04-02

申请号：US17131132

申请日：2020-12-22

Applicant: KYOCERA SLD Laser, Inc.

Inventor： Melvin McLaurin ,  James W. Raring

IPC: H01L33/00 ,  C30B29/40 ,  H01L21/02 ,  H01L21/784 ,  H01L33/12 ,  H01L33/32 ,  H01S5/02 ,  H01S5/02345 ,  H01S5/042 ,  H01S5/22 ,  H01S5/343

CPC classification number: H01S5/34333 ,  C30B29/406 ,  H01L21/02389 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/02631 ,  H01L21/02647 ,  H01L21/784 ,  H01L33/0045 ,  H01L33/0075 ,  H01L33/0093 ,  H01L33/12 ,  H01L33/32 ,  H01S5/0217 ,  H01S5/02345 ,  H01S5/0425 ,  H01S5/22 ,  H01S2304/02 ,  H01S2304/04

Abstract: The present disclosure provides a method and structure for producing large area gallium and nitrogen engineered substrate members configured for the epitaxial growth of layer structures suitable for the fabrication of high performance semiconductor devices. In a specific embodiment the engineered substrates are used to manufacture gallium and nitrogen containing devices based on an epitaxial transfer process wherein as-grown epitaxial layers are transferred from the engineered substrate to a carrier wafer for processing. In a preferred embodiment, the gallium and nitrogen containing devices are laser diode devices operating in the 390 nm to 425 nm range, the 425 nm to 485 nm range, the 485 nm to 550 nm range, or greater than 550 nm.