-
公开(公告)号：US07279950B2
公开(公告)日：2007-10-09
申请号：US11235758
申请日：2005-09-27
IPC分类号： H03K3/00
CPC分类号： G06F1/04
摘要： A differential clock signal gating method and system is provided, wherein a clock buffer circuit control path develops a clock gating signal with a timing relationship to a clock signal. The clock gating signal gates a buffer on the clock buffer circuit controlled path in communication with the clock signal responsive to a first clock signal pulse negative half. The buffer provides second and successive clock signal pulses occurring immediately and sequentially after the first clock signal pulse as a buffer clock signal output to a second buffer stage in a second stage clock path, each having the nominal clock amplitude and the nominal clock pulse width of the clock signal without jitter.
-
12.发明授权Circuit and method for reducing jitter in a PLL of high speed serial links 失效用于降低高速串行链路PLL的抖动的电路和方法公开(公告)号：US07042277B2
公开(公告)日：2006-05-09
申请号：US10685022
申请日：2003-10-14
IPC分类号： G01F1/10
CPC分类号： H03L7/10
摘要： Aspects for reducing jitter in a PLL of a high speed serial link include examining at least one parameter related to performance of a voltage controlled oscillator (VCO) in the PLL, and controlling adjustment of a supply voltage to the VCO based on the examining. A regulator control circuit performs the examining and controlling.
摘要翻译： 降低高速串行链路的PLL中的抖动的方面包括检查与PLL中的压控振荡器（VCO）的性能有关的至少一个参数，以及基于检查来控制对VCO的电源电压的调整。 调节器控制电路进行检查和控制。
-
13.发明授权One-sample-per-bit decision feedback equalizer (DFE) clock and data recovery 失效单采样每位决策反馈均衡器（DFE）时钟和数据恢复公开(公告)号：US07809054B2
公开(公告)日：2010-10-05
申请号：US11405997
申请日：2006-04-18
申请人： Juan A. Carballo , Hayden C. Cranford, Jr. , Gareth J. Nicholls , Vernon R. Norman , Martin L. Schmatz
发明人： Juan A. Carballo , Hayden C. Cranford, Jr. , Gareth J. Nicholls , Vernon R. Norman , Martin L. Schmatz
CPC分类号： H04L25/03063
摘要： Disclosed are a receiver circuit, method and design architecture of a decision feedback equalizer (DFE) Clock-And-Data Recovery (CDR) architecture that utilizes/produces one sample-per-bit in the receiver and reduces bit-error-rate (BER). An integrating receiver is combined with a decision feedback equalizer along with the appropriate (CDR) loop phase detector to maintain a single sample per bit requirement. The incoming voltage is converted to a current and connected to a current summing node. Weighted currents determined by the values of previously detected bits and their respective feedback coefficients are also connected to this node. Additionally, the summed currents is integrated and converted to a voltage. A sampler is utilized to make a bit decision based on the resulting voltage. After sampling, the integrator is reset before analysis of the next bit. The necessary amplification is achieved by maximizing the sensitivity of the latch, using integration in front of the data latch.
摘要翻译： 公开了一种在接收机中利用/产生一个每位采样的判决反馈均衡器（DFE）时钟和数据恢复（CDR）架构的接收器电路，方法和设计架构，并且降低了误码率（BER ）。 集成接收机与决策反馈均衡器以及适当的（CDR）环路相位检测器相结合，以保持每位需求的单个采样。 输入电压被转换为电流并连接到电流求和节点。 由先前检测到的位及其各自的反馈系数的值确定的加权电流也连接到该节点。 另外，总和电流被积分并转换成电压。 采样器用于基于所得到的电压进行位决定。 采样后，积分器在分析下一位之前被复位。 通过使用在数据锁存器前面的积分来最大化锁存器的灵敏度来实现必要的放大。
-
公开(公告)号：US07661052B2
公开(公告)日：2010-02-09
申请号：US12021950
申请日：2008-01-29
IPC分类号： G06F11/277 , G06F11/16
CPC分类号： G01R31/31901 , G01R31/31707
摘要： A method and system for testing a high-speed circuit is disclosed. The method and system include obtaining a high-speed statistical signature of the high-speed circuit using a conventional tester. The method and system further include comparing the high-speed statistical signature of the high-speed circuit to an expected signature. Consequently, it can be determined whether the high-speed circuit functions within the desired parameters.
摘要翻译： 公开了一种用于测试高速电路的方法和系统。 该方法和系统包括使用常规测试仪获得高速电路的高速统计特征。 该方法和系统还包括将高速电路的高速统计签名与预期签名进行比较。 因此，可以确定高速电路是否在期望的参数内起作用。
-
15.发明授权method for providing automatic adaptation to frequency offsets in high speed serial links 有权用于在高速串行链路中提供自动适应频率偏移的方法公开(公告)号：US07477713B2
公开(公告)日：2009-01-13
申请号：US10791175
申请日：2004-03-02
申请人： Hayden C. Cranford, Jr. , Gareth John Nicholls , Bobak Modaress-Razavi , Vernon R. Norman , Martin L. Schmatz
发明人： Hayden C. Cranford, Jr. , Gareth John Nicholls , Bobak Modaress-Razavi , Vernon R. Norman , Martin L. Schmatz
IPC分类号： H04L7/02
CPC分类号： H03L7/0814 , H03L7/07 , H04L2027/0065 , H04L2027/0067
摘要： Aspects of providing automatic adaptation to frequency offsets in high speed serial links are described. First signals for phase adjusts in a receiver link are adjusted by detecting trends in the first signals to generate second signals, the second signals improving a rate of compensation for the frequency offsets by the phase adjusts. An up/down counter is included for counting signals for phase adjustments by a clock-data-recovery loop of a serial receiver. An adder is coupled to the up/down counter and outputs accumulated data indicative of a trend in the phase adjustments. Combinatorial logic coupled to the adder adapts the signals based on the accumulated data.
摘要翻译： 描述了在高速串行链路中提供对频偏的自动适配的方面。 通过检测第一信号中的趋势来产生第二信号来调整在接收机链路中进行相位调整的第一信号，第二信号通过相位调整来提高对频偏的补偿率。 包括一个向上/向下计数器，用于通过串行接收器的时钟数据恢复环来对信号进行相位调整。 加法器耦合到上/下计数器并输出指示相位调整趋势的累加数据。 耦合到加法器的组合逻辑基于累积数据来适配信号。
-
公开(公告)号：US07315594B2
公开(公告)日：2008-01-01
申请号：US10484608
申请日：2002-07-15
IPC分类号： H04L7/00
CPC分类号： H03L7/091 , H03L7/0814 , H03L7/089 , H04L7/0331
摘要： The invention is directed to a clock data recovery system for resampling a clock signal to an incoming data signal. The clock data recovery system comprises a clock generator for generating the clock signal and a phase adjustment unit for generating sampling phases dependant on a phase adjustment control signal. It also comprises a data sampling unit operable to generate a stream of input samples and an edge detector for generating therefrom an internal early signal and an internal late signal. A phase adjustment control unit is disposed for generating under use of the early signal and the late signal the phase adjustment control signal. The phase adjustment control unit is feedable with an external early/late signal and/or comprises an output for delivering an export early/late signal.
摘要翻译： 本发明涉及一种用于将时钟信号重新采样到输入数据信号的时钟数据恢复系统。 时钟数据恢复系统包括用于产生时钟信号的时钟发生器和用于根据相位调整控制信号产生采样相位的相位调整单元。 它还包括可操作以产生输入样本流的数据采样单元和用于从其产生内部早期信号和内部迟滞信号的边缘检测器。 设置相位调整控制单元，用于在早期信号的使用下产生相位调整控制信号，并且延迟信号。 相位调整控制单元可以用外部早/晚信号进给，和/或包括用于传送出口早/晚信号的输出。
-
17.发明授权Method and system for providing quality control on wafers running on a manufacturing line 失效用于对在生产线上运行的晶片提供质量控制的方法和系统公开(公告)号：US07089132B2
公开(公告)日：2006-08-08
申请号：US10709805
申请日：2004-05-28
CPC分类号： G01R31/2831 , H01L22/14
摘要： A method for providing quality control on wafers running on a manufacturing line is disclosed. The resistances on a group of manufacturing test structures within a wafer running on a wafer manufacturing line are initially measured. Then, an actual distribution value is obtained based on the result of the measured resistances on the group of manufacturing test structures. The difference between the actual distribution value and a predetermined distribution value is recorded. Next, the resistances on a group of design test structures within the wafer are measured. The measured resistances of the group of design test structures are correlated to the measured resistances of the group of manufacturing test structures in order to obtain an offset value. The resistance of an adjustable resistor circuit within the wafer and subsequent wafers running on the wafer manufacturing line are adjusted according to the offset value.
摘要翻译： 公开了一种用于对在生产线上运行的晶片进行质量控制的方法。 初始测量在晶片生产线上运行的晶片内的一组制造测试结构的电阻。 然后，基于制造试验结构体的测定电阻的结果，求出实际的分布值。 记录实际分布值与预定分布值之间的差。 接下来，测量晶片内的一组设计测试结构的电阻。 设计测试结构组的测量电阻与制造测试结构组的测量电阻相关，以获得偏移值。 根据偏移值调整晶片内的可调节电阻电路和在晶片生产线上运行的随后的晶片的电阻。
-
公开(公告)号：US4748588A
公开(公告)日：1988-05-31
申请号：US810139
申请日：1985-12-18
CPC分类号： H04J3/062
摘要： A circuit arrangement for synchronizing source data from a source system with a clock and/or clocks from a sink system. The circuit arrangement includes a source counter, a buffer, a sink counter and a controller. The source data is placed in consecutive buffer positions under the control of the source counter. The sink counter is made to "follow" the source counter and identifies the location in the buffer whereat output data is to be extracted. The controller monitors the counters and generates control signals representative of the state of the buffer.
摘要翻译： 用于使来自源系统的源数据与来自sink系统的时钟和/或时钟同步的电路装置。 电路装置包括源计数器，缓冲器，汇计数器和控制器。 源数据位于源计数器控制下的连续缓冲位置。 宿计数器用于“跟踪”源计数器，并标识要在其中提取输出数据的缓冲器中的位置。 控制器监视计数器并产生代表缓冲器状态的控制信号。
-
19.发明申请CIRCUIT FOR PROVIDING AUTOMATIC ADAPTATION TO FREQUENCY OFFSETS IN HIGH SPEED SERIAL LINKS 审中-公开提供自动适应高速串行链路频率偏移的电路公开(公告)号：US20090116593A1
公开(公告)日：2009-05-07
申请号：US12349385
申请日：2009-01-06
申请人： HAYDEN C. CRANFORD, JR. , GARETH JOHN NICHOLLS , BOBAK MODARESS-RAZAVI , VERNON R. NORMAN , MARTIN L. SCHMATZ
发明人： HAYDEN C. CRANFORD, JR. , GARETH JOHN NICHOLLS , BOBAK MODARESS-RAZAVI , VERNON R. NORMAN , MARTIN L. SCHMATZ
IPC分类号： H04L7/02
CPC分类号： H03L7/0814 , H03L7/07 , H04L2027/0065 , H04L2027/0067
摘要： Aspects of providing automatic adaptation to frequency offsets in high speed serial links are described. First signals for phase adjusts in a receiver link are adjusted by detecting trends in the first signals to generate second signals, the second signals improving a rate of compensation for the frequency offsets by the phase adjusts. An up/down counter is included for counting signals for phase adjustments by a clock-data-recovery loop of a serial receiver. An adder is coupled to the up/down counter and outputs accumulated data indicative of a trend in the phase adjustments. Combinatorial logic coupled to the adder adapts the signals based on the accumulated data.
摘要翻译： 描述了在高速串行链路中提供对频偏的自动适配的方面。 通过检测第一信号中的趋势来产生第二信号来调整在接收机链路中进行相位调整的第一信号，第二信号通过相位调整来提高对频偏的补偿率。 包括一个向上/向下计数器，用于通过串行接收器的时钟数据恢复环来对信号进行相位调整。 加法器耦合到上/下计数器并输出指示相位调整趋势的累加数据。 耦合到加法器的组合逻辑基于累积数据来适配信号。
-
20.发明申请公开(公告)号：US20080120838A1
公开(公告)日：2008-05-29
申请号：US12028439
申请日：2008-02-08
申请人： Steven M. Clements , William P. Cornwell , Carrie E. Cox , Hayden C. Cranford , Vernon R. Norman
发明人： Steven M. Clements , William P. Cornwell , Carrie E. Cox , Hayden C. Cranford , Vernon R. Norman
IPC分类号： H01R43/00
CPC分类号： G01R35/007 , Y10T29/49004 , Y10T29/4913 , Y10T29/49147 , Y10T29/49155 , Y10T29/49169 , Y10T29/49174
摘要： Substantially-accurate calibration of output impedance of a device-under-test (DUT) to within a predetermined range of allowable impedance. The DUT is part of a source series terminated (SST) serial link transmitter, in which two branches of parallel transistors each provide an impedance value when particular transistors of the parallel branch are turned on. The impedance value is added to a series-connected resistor to provide the output impedance. The DUT consists of one branch of parallel transistors in series with a resistor. Output impedance of the DUT is compared to the resistance of a reference resistor, and the comparator provides a control signal based on whether the output impedance falls within the pre-set percentage variance of the reference resistance. The control signal is processed by a FSM (finite state machine) that individually turns on or off the transistors within the parallel branch until the DUT impedance value falls within the desired range.
摘要翻译： 将被测器件（DUT）的输出阻抗基本上精确地校准到允许阻抗的预定范围内。 DUT是源极串行端接（SST）串行链路发射机的一部分，其中当并联支路的特定晶体管导通时，并联晶体管的两个分支都提供阻抗值。 将阻抗值加到串联电阻器上以提供输出阻抗。 DUT由与电阻器串联的并行晶体管的一个分支组成。 将DUT的输出阻抗与参考电阻的电阻进行比较，并且比较器根据输出阻抗是否落在参考电阻的预设百分比方差内提供控制信号。 控制信号由FSM（有限状态机）进行处理，FSM单独打开或关闭并联支路内的晶体管，直到DUT阻抗值落在所需范围内。
-
-
-
-
-
-
-
-
-
搜索结果
31 条记录 (耗时 0.018 秒)
