公开(公告)号：US20070047292A1

公开(公告)日：2007-03-01

申请号：US11444295

申请日：2006-05-31

申请人： Joerg Berthold ,  Dieter Draxelmayr ,  Winfried Kamp ,  Michael Kund ,  Tim Schoenauer

发明人： Joerg Berthold ,  Dieter Draxelmayr ,  Winfried Kamp ,  Michael Kund ,  Tim Schoenauer

IPC分类号： G11C11/00

CPC分类号： G11C13/0011 ,  G11C13/0004 ,  G11C14/009

摘要： Nonvolatile memory cell, having a first resistor that is electrically programmable in a nonvolatile fashion, a second resistor that is electrically programmable in a nonvolatile fashion, a first leakage current reducing element connected between the first resistor and an operating potential, and a second leakage current reducing element connected between the second resistor and the operating potential.

摘要翻译： 具有以非易失性方式电可编程的第一电阻器的非易失性存储器单元，以非易失性方式电可编程的第二电阻器，连接在第一电阻器和工作电位之间的第一漏电流减少元件和第二漏电流 连接在第二电阻和工作电位之间的减少元件。

公开(公告)号：US20050204274A1

公开(公告)日：2005-09-15

申请号：US11063953

申请日：2005-02-23

申请人： Winfried Kamp ,  Siegmar Koppe

发明人： Winfried Kamp ,  Siegmar Koppe

IPC分类号： G06F11/00 ,  G06F11/10 ,  G11C29/00 ,  H03M13/00

CPC分类号： G11C15/04 ,  G06F11/1048 ,  G11C15/00 ,  G11C2029/0411

摘要： A parity checking circuit is designed for continuous parity checking of content-addressable memory cells, and is configured such that during a parity check the number of parity checking steps per data word is the same as the number of bits in the original payload data word to be stored, with the parity checking circuit being formed from four transistors of the same conductance type. The parity checking circuit has a detector, which automatically detects the change in an information state of a memory cell. The detector is in the form of an automatic state device and has a number of catch latches.

摘要翻译： 奇偶校验电路被设计用于可内容寻址存储器单元的连续奇偶校验，并且被配置为使得在奇偶校验期间，每个数据字的奇偶校验步骤的数量与原始有效载荷数据字中的位数相同 存储奇偶校验电路由相同电导型的四个晶体管形成。 奇偶校验电路具有检测器，其自动检测存储器单元的信息状态的变化。 检测器是自动状态设备的形式，并具有多个锁存器。

公开(公告)号：US08854866B2

公开(公告)日：2014-10-07

申请号：US13163131

申请日：2011-06-17

申请人： Peter Huber ,  Winfried Kamp ,  Joel Hatsch ,  Michel d'Argouges ,  Siegmar Koeppe ,  Thomas Kuenemund

发明人： Peter Huber ,  Winfried Kamp ,  Joel Hatsch ,  Michel d'Argouges ,  Siegmar Koeppe ,  Thomas Kuenemund

IPC分类号： G11C11/00 ,  G06F21/72 ,  H04L9/08

CPC分类号： H04L9/0866 ,  G06F21/72

摘要： A semiconductor device includes an identification circuit. The identification circuit includes a memory cell which includes a first transistor having a first value of a switching characteristic and a second transistor having a second value of the switching characteristic. The identification circuit is operable to generate a memory-cell-specific identification bit which is dependent on production-dictated differences in the first switching characteristic of the first transistor and the second switching characteristic of the second transistor. The identification circuit further includes a drive circuit for the memory cell. The drive circuit is operable to connect or isolate an upper supply potential and a lower supply potential of the semiconductor device to or from the memory cell independently of one another.

摘要翻译： 半导体器件包括识别电路。 识别电路包括存储单元，其包括具有第一开关特性值的第一晶体管和具有第二开关特性值的第二晶体管。 识别电路可操作以产生依赖于第一晶体管的第一开关特性和第二晶体管的第二开关特性中生产规定的差异的存储单元特定的识别位。 识别电路还包括用于存储单元的驱动电路。 驱动电路可操作以独立于彼此连接或隔离半导体器件的上电源电位和较低电源电压到存储器单元或从存储器单元隔离。

公开(公告)号：US20120020145A1

公开(公告)日：2012-01-26

申请号：US13163131

申请日：2011-06-17

申请人： Peter Huber ,  Winfried Kamp ,  Joel Hatsch ,  Michel d'Argouges ,  Siegmar Koeppe

发明人： Peter Huber ,  Winfried Kamp ,  Joel Hatsch ,  Michel d'Argouges ,  Siegmar Koeppe

IPC分类号： G11C11/40 ,  G11C8/08

CPC分类号： H04L9/0866 ,  G06F21/72

摘要： A semiconductor device includes an identification circuit. The identification circuit includes a memory cell which includes a first transistor having a first value of a switching characteristic and a second transistor having a second value of the switching characteristic. The identification circuit is operable to generate a memory-cell-specific identification bit which is dependent on production-dictated differences in the first switching characteristic of the first transistor and the second switching characteristic of the second transistor. The identification circuit further includes a drive circuit for the memory cell. The drive circuit is operable to connect or isolate an upper supply potential and a lower supply potential of the semiconductor device to or from the memory cell independently of one another.

摘要翻译： 半导体器件包括识别电路。 识别电路包括存储单元，其包括具有第一开关特性值的第一晶体管和具有第二开关特性值的第二晶体管。 识别电路可操作以产生依赖于第一晶体管的第一开关特性和第二晶体管的第二开关特性中生产规定的差异的存储单元特定的识别位。 识别电路还包括用于存储单元的驱动电路。 驱动电路可操作以独立于彼此连接或隔离半导体器件的上电源电位和较低电源电压到存储器单元或从存储器单元隔离。

公开(公告)号：US20100329446A1

公开(公告)日：2010-12-30

申请号：US11462144

申请日：2006-08-03

申请人： Antoine Degrendel ,  Winfried Kamp ,  Manfred Roth ,  Thomas Kodytek

发明人： Antoine Degrendel ,  Winfried Kamp ,  Manfred Roth ,  Thomas Kodytek

IPC分类号： H04L9/28

CPC分类号： H03K19/0948 ,  G06F7/00 ,  G06F21/755 ,  G06F2207/7238 ,  G06F2207/7266

摘要： A logic circuit for calculating an encrypted dual-rail result operand from encrypted dual-rail input operands according to a combination rule includes inputs for receiving the input operands and an output for outputting the encrypted result operand. Each operand may comprise a first logic state or a second logic state. The logic circuit comprises a first logic stage connected between the inputs and an intermediate node and a second logic stage connected between the intermediate node and the output. The logic stages are formed to calculate the first or second logic state of the encrypted result operand from the input operands according to the combination rule and to maintain or change exactly once the logic state of the encrypted result operand, independently of an order of arrival of the encrypted input operands, depending on the combination rule, in order to impress the calculated first logic state or second logic state on the output.

摘要翻译： 用于根据组合规则从加密的双轨输入操作数计算加密的双轨结果操作数的逻辑电路包括用于接收输入操作数的输入和用于输出加密结果操作数的输出。 每个操作数可以包括第一逻辑状态或第二逻辑状态。 逻辑电路包括连接在输入与中间节点之间的第一逻辑级和连接在中间节点与输出之间的第二逻辑级。 逻辑级被形成为根据组合规则从输入操作数计算加密结果操作数的第一或第二逻辑状态，并且只要一旦加密结果操作数的逻辑状态独立于维护或更改 加密的输入操作数，取决于组合规则，以便将计算出的第一逻辑状态或第二逻辑状态置于输出上。

公开(公告)号：US07509561B2

公开(公告)日：2009-03-24

申请号：US11063953

申请日：2005-02-23

申请人： Winfried Kamp ,  Siegmar Köppe

发明人： Winfried Kamp ,  Siegmar Köppe

IPC分类号： H03M13/00

CPC分类号： G11C15/04 ,  G06F11/1048 ,  G11C15/00 ,  G11C2029/0411

摘要： A parity checking circuit is designed for continuous parity checking of content-addressable memory cells, and is configured such that during a parity check the number of parity checking steps per data word is the same as the number of bits in the original payload data word to be stored, with the parity checking circuit being formed from four transistors of the same conductance type. The parity checking circuit has a detector, which automatically detects the change in an information state of a memory cell. The detector is in the form of an automatic state device and has a number of catch latches.

摘要翻译： 奇偶校验电路被设计用于可内容寻址存储器单元的连续奇偶校验，并且被配置为使得在奇偶校验期间，每个数据字的奇偶校验步骤的数量与原始有效载荷数据字中的位数相同 存储奇偶校验电路由相同电导型的四个晶体管形成。 奇偶校验电路具有检测器，其自动检测存储器单元的信息状态的变化。 检测器是自动状态设备的形式，并具有多个锁存器。

公开(公告)号：US20090014806A1

公开(公告)日：2009-01-15

申请号：US11775504

申请日：2007-07-10

申请人： Martin Ostermayr ,  Winfried Kamp ,  Anton Huber

发明人： Martin Ostermayr ,  Winfried Kamp ,  Anton Huber

IPC分类号： H01L29/94 ,  H01L21/8238

CPC分类号： H01L21/823807 ,  H01L27/0207 ,  H01L27/1104

摘要： A semiconductor device and method of manufacturing thereof. The semiconductor device has at least one NMOS device and at least one PMOS device provided on a substrate. An electron channel of the NMOS device is aligned with a first direction. A hole channel of the PMOS device is aligned with a different second direction that forms an acute angle with respect to the first direction.

摘要翻译： 一种半导体器件及其制造方法。 半导体器件具有至少一个NMOS器件和设置在衬底上的至少一个PMOS器件。 NMOS器件的电子通道与第一方向对准。 PMOS器件的空穴通道与形成相对于第一方向的锐角的不同的第二方向对齐。

公开(公告)号：US07436694B2

公开(公告)日：2008-10-14

申请号：US11444295

申请日：2006-05-31

申请人： Joerg Berthold ,  Dieter Draxelmayr ,  Winfried Kamp ,  Michael Kund ,  Tim Schoenauer

发明人： Joerg Berthold ,  Dieter Draxelmayr ,  Winfried Kamp ,  Michael Kund ,  Tim Schoenauer

IPC分类号： G11C11/00

CPC分类号： G11C13/0011 ,  G11C13/0004 ,  G11C14/009

摘要： Nonvolatile memory cell, having a first resistor that is electrically programmable in a nonvolatile fashion, a second resistor that is electrically programmable in a nonvolatile fashion, a first leakage current reducing element connected between the first resistor and an operating potential, and a second leakage current reducing element connected between the second resistor and the operating potential.

摘要翻译： 具有以非易失性方式电可编程的第一电阻器的非易失性存储器单元，以非易失性方式电可编程的第二电阻器，连接在第一电阻器和工作电位之间的第一漏电流减少元件和第二漏电流 连接在第二电阻和工作电位之间的减少元件。

公开(公告)号：US20070030031A1

公开(公告)日：2007-02-08

申请号：US11461935

申请日：2006-08-02

申请人： Antoine Degrendel ,  Winfried Kamp ,  Manfred Roth

发明人： Antoine Degrendel ,  Winfried Kamp ,  Manfred Roth

IPC分类号： H03K19/096

CPC分类号： H03K19/0963 ,  G06F21/755 ,  H04L9/003 ,  H04L2209/046 ,  H04L2209/12

摘要： Circuit for calculating a logic combination of two encrypted input operands receivese first and second dual-rail signals comprising data values in a calculation cycle and precharge values in a precharge cycle, and receives a dual-rail encryption signal comprising encryption values in the calculation cycle and precharge values in the precharge cycle, and outputs a dual-rail result signal comprising encrypted result values in the calculation cycle and precharge values in the precharge cycle. The data and encrypted result values are encrypted with the encryption values of the dual-rail encryption signal according to an encryption rule. A logic circuit determines the encrypted result values according to the logic combination from the data and encryption values, and outputs the encrypted result values in the calculation cycle. A precharge circuit impresses precharge values when precharge values are sensed at a single input, or impresses the precharge values only when the first and second dual-rail signals comprise data values and the dual-rail encryption signal comprises encryption values.

摘要翻译： 用于计算两个加密输入操作数的逻辑组合的电路接收第一和第二双轨信号，其包括计算周期中的数据值和预充电周期中的预充电值，并且接收包括计算周期中的加密值的双轨加密信号，以及 在预充电循环中预充电值，并且在计算周期中输出包括加密结果值的双轨结果信号和预充电循环中的预充电值。 数据和加密结果值根据加密规则用双轨加密信号的加密值进行加密。 逻辑电路根据来自数据和加密值的逻辑组合确定加密结果值，并在计算周期中输出加密的结果值。 当在单个输入处感测到预充电值时，预充电电路给予预充电值，或者仅当第一和第二双轨信号包括数据值并且双轨加密信号包括加密值时，才施加预充电值。

公开(公告)号：US20050114424A1

公开(公告)日：2005-05-26

申请号：US10961521

申请日：2004-10-08

申请人： Joel Hatsch ,  Winfried Kamp

发明人： Joel Hatsch ,  Winfried Kamp

IPC分类号： G06F7/50 ,  G06F7/60 ,  H03K19/21 ,  H03K19/23

CPC分类号： G06F7/607 ,  H03K19/215 ,  H03K19/23

摘要： The invention relates to an adder for adding at least four bits of the same significance w, said adder having a first number of inputs for receiving the bits of the same significance w that are to be added and a number of outputs, the bits to be added being applied to the inputs in presorted form, and the adder adding the bits while taking account of the presorting. The invention also provides an adding device for adding at least four bits of equal significance and a corresponding method.

摘要翻译： 本发明涉及一种加法器，用于将相同含义w的至少四个比特相加，所述加法器具有第一数量的输入，用于接收与要相加的相同含义w的比特和多个输出， 以预分解形式将其应用于输入，加法器在考虑到预分频时加入位。 本发明还提供了一种用于添加至少四位具有相同重要性的添加装置和相应的方法。