公开(公告)号：US20060177998A1

公开(公告)日：2006-08-10

申请号：US11379435

申请日：2006-04-20

Applicant: Ming-Ren Lin ,  Witold Maszara ,  Haihong Wang ,  Bin Yu

Inventor： Ming-Ren Lin ,  Witold Maszara ,  Haihong Wang ,  Bin Yu

IPC: H01L21/3205

CPC classification number: H01L29/785 ,  H01L29/4908 ,  H01L29/66795 ,  H01L29/7842

Abstract: A method may include forming a gate electrode over a fin structure, depositing a first metal layer on a top surface of the gate electrode, performing a first silicide process to convert a portion of the gate electrode into a metal-silicide compound, depositing a second metal layer on a top surface of the metal-silicide compound, and performing a second silicide process to form a fully-silicided gate electrode.

Abstract translation: 一种方法可以包括在鳍结构上形成栅电极，在栅电极的顶表面上沉积第一金属层，执行第一硅化工艺以将栅电极的一部分转化为金属硅化物， 在金属硅化物化合物的顶表面上的金属层，并且执行第二硅化物处理以形成全硅化物栅电极。

公开(公告)号：US20050048743A1

公开(公告)日：2005-03-03

申请号：US10654497

申请日：2003-09-03

Applicant: Ihsan Djomehri ,  Jung-Suk Goo ,  Srinath Krishnan ,  Witold Maszara ,  James Pan ,  Qi Xiang

Inventor： Ihsan Djomehri ,  Jung-Suk Goo ,  Srinath Krishnan ,  Witold Maszara ,  James Pan ,  Qi Xiang

IPC: H01L21/20 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L29/0847 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/78

Abstract: A method of forming a channel region for a transistor includes forming a layer of silicon germanium (SiGe) above a substrate, forming an oxide layer above the SiGe layer wherein the oxide layer includes an aperture in a channel area and the aperture is filled with a SiGe feature, depositing a layer having a first thickness above the oxide layer and the SiGe feature, and forming source and drain regions in the layer.

Abstract translation: 形成用于晶体管的沟道区的方法包括在衬底上形成硅锗层（SiGe），在SiGe层上形成氧化物层，其中氧化物层包括沟道区中的孔，并且孔填充有 SiGe特征，在氧化物层上沉积具有第一厚度的层和SiGe特征，以及在该层中形成源区和漏区。

公开(公告)号：US20130005114A1

公开(公告)日：2013-01-03

申请号：US13611193

申请日：2012-09-12

Applicant: Witold MASZARA ,  Hemant ADHIKARI

Inventor： Witold MASZARA ,  Hemant ADHIKARI

IPC: H01L21/762

CPC classification number: H01L29/785 ,  H01L29/66795

Abstract: Methods are provided for fabricating a semiconductor device. A method comprises forming a layer of a first semiconductor material overlying the bulk substrate and forming a layer of a second semiconductor material overlying the layer of the first semiconductor material. The method further comprises creating a fin pattern mask on the layer of the second semiconductor material and anisotropically etching the layer of the second semiconductor material and the layer of the first semiconductor material using the fin pattern mask as an etch mask. The anisotropic etching results in a fin formed from the second semiconductor material and an exposed region of first semiconductor material underlying the fin. The method further comprises forming an isolation layer in the exposed region of first semiconductor material underlying the fin.

Abstract translation: 提供了制造半导体器件的方法。 一种方法包括形成覆盖在本体衬底上的第一半导体材料层，并形成覆盖第一半导体材料层的第二半导体材料层。 该方法还包括在第二半导体材料的层上形成鳍状图案掩模，并使用鳍状图案掩模作为蚀刻掩模，各向异性蚀刻第二半导体材料的层和第一半导体材料的层。 各向异性蚀刻导致由第二半导体材料形成的翅片和鳍下方的第一半导体材料的暴露区域。 该方法还包括在鳍片下方的第一半导体材料的暴露区域中形成隔离层。

公开(公告)号：US20100248454A1

公开(公告)日：2010-09-30

申请号：US12413174

申请日：2009-03-27

Applicant: Witold MASZARA ,  Ming-Ren LIN ,  Jin CHO ,  Zoran KRIVOKAPIC

Inventor： Witold MASZARA ,  Ming-Ren LIN ,  Jin CHO ,  Zoran KRIVOKAPIC

IPC: H01L21/20 ,  H01L21/28

CPC classification number: H01L29/66795

Abstract: A method of manufacturing semiconductor fins for a semiconductor device may begin by providing a bulk semiconductor substrate. The method continues by growing a layer of first epitaxial semiconductor material on the bulk semiconductor substrate, and by growing a layer of second epitaxial semiconductor material on the layer of first epitaxial semiconductor material. The method then creates a fin pattern mask on the layer of second epitaxial semiconductor material. The fin pattern mask has features corresponding to a plurality of fins. Next, the method anisotropically etches the layer of second epitaxial semiconductor material, using the fin pattern mask as an etch mask, and using the layer of first epitaxial semiconductor material as an etch stop layer. This etching step results in a plurality of fins formed from the layer of second epitaxial semiconductor material.

Abstract translation: 制造用于半导体器件的半导体鳍片的方法可以通过提供体半导体衬底开始。 该方法通过在体半导体衬底上生长第一外延半导体材料层并通过在第一外延半导体材料层上生长第二外延半导体材料层来继续。 该方法然后在第二外延半导体材料层上产生鳍状图案掩模。 翅片图形掩模具有对应于多个翅片的特征。 接下来，使用鳍图案掩模作为蚀刻掩模，并且使用第一外延半导体材料层作为蚀刻停止层，该方法各向异性地蚀刻第二外延半导体材料的层。 该蚀刻步骤导致由第二外延半导体材料层形成的多个鳍片。

公开(公告)号：US20060211245A1

公开(公告)日：2006-09-21

申请号：US11422811

申请日：2006-06-07

Applicant: Witold Maszara

Inventor： Witold Maszara

IPC: H01L21/336 ,  H01L21/4763 ,  H01L21/44

CPC classification number: H01L29/78 ,  H01L21/2652 ,  H01L21/28518 ,  H01L29/41775 ,  H01L29/665 ,  H01L29/66628

Abstract: A method of forming an abrupt junction device with a semiconductor substrate is provided. A gate dielectric is formed on a semiconductor substrate, and a gate is formed on the gate dielectric. A sidewall spacer is formed on the semiconductor substrate adjacent the gate and the gate dielectric. A thickening layer is formed by selective epitaxial growth on the semiconductor substrate adjacent the sidewall spacer. Raised source/drain dopant implanted regions are formed in at least a portion of the thickening layer. Silicide layers are formed in at least a portion of the raised source/drain dopant implanted regions to form source/drain regions, beneath the silicide layers, that are enriched with dopant from the silicide layers. A dielectric layer is deposited over the silicide layers, and contacts are then formed in the dielectric layer to the silicide layers.

Abstract translation: 提供了一种形成具有半导体衬底的突点连接器件的方法。 在半导体衬底上形成栅极电介质，在栅极电介质上形成栅极。 在与栅极和栅极电介质相邻的半导体衬底上形成侧壁间隔物。 通过在邻近侧壁间隔物的半导体衬底上选择性外延生长形成增厚层。 在增稠层的至少一部分形成凸起的源/漏掺杂剂注入区。 在升高的源极/漏极掺杂剂注入区域的至少一部分中形成硅化物层，以在硅化物层下面形成源极/漏极区域，其从硅化物层富集掺杂剂。 在硅化物层上沉积电介质层，然后在电介质层中形成接触到硅化物层。

公开(公告)号：US20050048727A1

公开(公告)日：2005-03-03

申请号：US10654631

申请日：2003-09-03

Applicant: Witold Maszara ,  Jung-Suk Goo ,  James Pan ,  Qi Xiang

Inventor： Witold Maszara ,  Jung-Suk Goo ,  James Pan ,  Qi Xiang

IPC: A61F5/37 ,  H01L21/336 ,  H01L29/10 ,  H01L29/786

CPC classification number: H01L29/785 ,  A61F5/3776 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/78687 ,  Y10S438/933

Abstract: A method of forming a finFET transistor using a sidewall epitaxial layer includes forming a silicon germanium (SiGe) layer above an oxide layer above a substrate, forming a cap layer above the SiGe layer, removing portions of the SiGe layer and the cap layer to form a feature, forming sidewalls along lateral walls of the feature, and removing the feature.

Abstract translation: 使用侧壁外延层形成finFET晶体管的方法包括在衬底上方的氧化层上形成硅锗（SiGe）层，在SiGe层上方形成覆盖层，去除SiGe层和覆盖层的部分以形成 特征，沿着所述特征的侧壁形成侧壁，以及去除所述特征。

公开(公告)号：US06399452B1

公开(公告)日：2002-06-04

申请号：US09612200

申请日：2000-07-08

Applicant: Srinath Krishnan ,  Witold Maszara

Inventor： Srinath Krishnan ,  Witold Maszara

IPC: H01L21336

CPC classification number: H01L29/6659 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/324

Abstract: A low thermal budget transistor is fabricated by first forming a gate on a semiconductor substrate. First amorphous regions and first inactive dopant regions are then created in the substrate by ion implantation. Sidewall spacers, which align subsequent implantation steps, are formed adjacent to the gate. Thereafter, second amorphous regions and second inactive dopant regions are created in the substrate by ion implantation. Dopants in the first and second inactive dopant regions are then activated using a low temperature annealing process to create source/drain regions and source/drain extension regions. The aforementioned process simplifies the fabrication of a low thermal budget transistor by dispensing with the requirement to remove the sidewall spacers.

Abstract translation: 通过首先在半导体衬底上形成栅极来制造低热​​预算晶体管。 然后通过离子注入在衬底中产生第一非晶区域和第一非活性掺杂剂区域。 对准随后的注入步骤的侧壁间隔件邻近门形成。 此后，通过离子注入在衬底中产生第二非晶区域和第二非活性掺杂剂区域。 然后使用低温退火工艺激活第一和第二非活性掺杂剂区域中的掺杂剂，以产生源极/漏极区域和源极/漏极延伸区域。 上述过程通过分配去除侧壁间隔物的要求简化了低热预算晶体管的制造。

公开(公告)号：US08859389B2

公开(公告)日：2014-10-14

申请号：US13015857

申请日：2011-01-28

Applicant: Hirohisa Kawasaki ,  Basker Veeraraghavan ,  Hemant Adhikari ,  Witold Maszara

Inventor： Hirohisa Kawasaki ,  Basker Veeraraghavan ,  Hemant Adhikari ,  Witold Maszara

IPC: H01L21/76 ,  H01L21/336 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L29/785

Abstract: Methods of making fins and semiconductor structures containing fins are provided. The methods involve forming a multi-layer structure over a semiconductor substrate. The multi-layer structure comprises a first layer over the semiconductor substrate, a second layer over the first layer, and a third layer over the second layer. The method also comprises removing upper portions of the semiconductor substrate and portions of the multi-layer structure to form fins of the semiconductor substrate and portions of the multi-layer structure. Further, the method comprises selectively oxidizing the first layer while oxidization of the second layer and the third layer is less than the oxidization of the first layer. The oxidation can be performed before gap fill recess or after gap fill recess.

Abstract translation: 提供制造散热片和包含散热片的半导体结构的方法。 所述方法包括在半导体衬底上形成多层结构。 多层结构包括半导体衬底上的第一层，第一层上的第二层和第二层上的第三层。 该方法还包括去除半导体衬底的上部和多层结构的部分以形成半导体衬底的鳍片和多层结构的部分。 此外，该方法包括选择性地氧化第一层，同时氧化第二层，第三层小于第一层的氧化。 可以在间隙填充凹部之前或间隙填充凹部之后进行氧化。

公开(公告)号：US08466034B2

公开(公告)日：2013-06-18

申请号：US12749220

申请日：2010-03-29

Applicant: Witold Maszara ,  Robert J. Miller

Inventor： Witold Maszara ,  Robert J. Miller

IPC: H01L21/76

CPC classification number: H01L29/66545 ,  H01L29/66795

Abstract: A method of manufacturing a finned semiconductor device structure is provided. The method begins by providing a substrate having bulk semiconductor material. The method continues by forming a semiconductor fin structure from the bulk semiconductor material, depositing an insulating material overlying the semiconductor fin structure such that the insulating material fills space adjacent to the semiconductor fin structure, and planarizing the deposited insulating material and the semiconductor fin structure to create a flat surface. Thereafter, a replacement gate procedure is performed to form a gate structure transversely overlying the semiconductor fin structure.

Abstract translation: 提供一种制造翅片半导体器件结构的方法。 该方法开始于提供具有体半导体材料的衬底。 该方法继续通过从体半导体材料形成半导体鳍结构，沉积覆盖半导体鳍结构的绝缘材料，使得绝缘材料填充与半导体鳍结构相邻的空间，并将沉积的绝缘材料和半导体鳍结构平坦化为 创建一个平坦的表面。 此后，执行替换门程序以形成横向覆盖半导体鳍结构的栅极结构。

公开(公告)号：US08334177B2

公开(公告)日：2012-12-18

申请号：US13278010

申请日：2011-10-20

Applicant: Witold Maszara ,  Hemant Adhikari

Inventor： Witold Maszara ,  Hemant Adhikari

IPC: H01L21/84 ,  H01L21/8238 ,  H01L21/336

CPC classification number: H01L29/785 ,  H01L29/66795

Abstract: Methods are provided for fabricating a semiconductor device. A method comprises forming a layer of a first semiconductor material overlying the bulk substrate and forming a layer of a second semiconductor material overlying the layer of the first semiconductor material. The method further comprises creating a fin pattern mask on the layer of the second semiconductor material and anisotropically etching the layer of the second semiconductor material and the layer of the first semiconductor material using the fin pattern mask as an etch mask. The anisotropic etching results in a fin formed from the second semiconductor material and an exposed region of first semiconductor material underlying the fin. The method further comprises forming an isolation layer in the exposed region of first semiconductor material underlying the fin.

Abstract translation: 提供了制造半导体器件的方法。 一种方法包括形成覆盖在本体衬底上的第一半导体材料层，并形成覆盖第一半导体材料层的第二半导体材料层。 该方法还包括在第二半导体材料的层上形成鳍状图案掩模，并使用鳍状图案掩模作为蚀刻掩模，各向异性蚀刻第二半导体材料的层和第一半导体材料的层。 各向异性蚀刻导致由第二半导体材料形成的翅片和鳍下方的第一半导体材料的暴露区域。 该方法还包括在鳍片下方的第一半导体材料的暴露区域中形成隔离层。