CARRIER TAPE FEEDER
    11.
    发明申请
    CARRIER TAPE FEEDER 有权
    载体胶带进纸器

    公开(公告)号:US20110243695A1

    公开(公告)日:2011-10-06

    申请号:US12985642

    申请日:2011-01-06

    IPC分类号: H05K13/02 H05K13/04 B65H5/28

    摘要: A carrier tape feeder is provided. The carrier tape feeder includes a unit for loading a carrier tape, a picking-up unit where chips are picked up, and a driving unit. The pick-up unit includes a knife portion, a folding-guiding portion, and an inversion-guiding portion. The knife portion separates a cover tape from a base tape in a first adhesive portion. The folding-guiding portion is spaced from one lateral side of the knife portion to induce folding of the cover tape separated by the knife portion in the lengthwise direction in a state in which the cover tape is partially attached to the base tape in a second adhesive portion. The inversion-guiding portion extends in an oblique direction from the knife portion and the folding-guiding portion toward the outside of the carrier tape to induce inversion of the upper and lower surfaces of the cover tape folded in the folding-guiding portion so as to be superimposed on the base tape. The distal end of the lateral side of the folding-guiding portion opposed to the knife portion extends above the second adhesive portion.

    摘要翻译: 提供载带输送机。 载带馈送器包括用于装载载带的单元,拾取芯片的拾取单元和驱动单元。 拾取单元包括刀部,折叠引导部和反转引导部。 刀部分在第一粘合剂部分中将盖带与基带分离。 折叠引导部分与刀部分的一个横向侧面间隔开,以便在第二粘合剂中将盖带部分地附接到基带的状态下,沿长度方向引导由刀片部分分开的盖带的折叠 一部分。 反转引导部分从刀部分和折叠引导部分的倾斜方向向载带的外侧延伸以引起折叠在折叠引导部分中的盖带的上表面和下表面的反转,从而 叠加在基带上。 折叠引导部分的与刀部相对的侧面的远端在第二粘合部分的上方延伸。

    METAL OXIDE SEMICONDUCTOR (MOS) TRANSISTORS HAVING A RECESSED GATE ELECTRODE
    12.
    发明申请
    METAL OXIDE SEMICONDUCTOR (MOS) TRANSISTORS HAVING A RECESSED GATE ELECTRODE 有权
    带有电极的金属氧化物半导体(MOS)晶体管

    公开(公告)号:US20100102384A1

    公开(公告)日:2010-04-29

    申请号:US12683089

    申请日:2010-01-06

    IPC分类号: H01L29/78

    摘要: A metal oxide semiconductor (MOS) includes an isolation layer disposed in a semiconductor substrate to define an active region. A source region and a drain region are disposed on both sides of the active region such that a first direction is defined from the source region to the drain region. A channel recess is disposed in the active region between the source and drain regions. The channel recess has a convex surface when viewed from a cross-sectional view taken along a second direction orthogonal to the first direction. A gate electrode fills the channel recess and crosses the active region in the second direction. A gate insulating layer is interposed between the gate electrode and the active region.

    摘要翻译: 金属氧化物半导体(MOS)包括设置在半导体衬底中以限定有源区的隔离层。 源极区域和漏极区域设置在有源区域的两侧,使得从源极区域到漏极区域限定第一方向。 通道凹槽设置在源区和漏区之间的有源区中。 当从沿着与第一方向正交的第二方向截取的横截面视图观察时,通道凹部具有凸形表面。 栅电极填充通道凹槽并沿第二方向跨过有源区。 栅极绝缘层插入在栅电极和有源区之间。

    Metal oxide semiconductor (MOS) transistor having a recessed gate electrode and methods of fabricating the same
    13.
    发明授权
    Metal oxide semiconductor (MOS) transistor having a recessed gate electrode and methods of fabricating the same 有权
    具有凹陷栅电极的金属氧化物半导体(MOS)晶体管及其制造方法

    公开(公告)号:US07655522B2

    公开(公告)日:2010-02-02

    申请号:US11263434

    申请日:2005-10-31

    IPC分类号: H01L21/336

    摘要: A metal oxide semiconductor (MOS) includes an isolation layer disposed in a semiconductor substrate to define an active region. A source region and a drain region are disposed on both sides of the active region such that a first direction is defined from the source region to the drain region. A channel recess is disposed in the active region between the source and drain regions. The channel recess has a convex surface when viewed from a cross-sectional view taken along a second direction orthogonal to the first direction. A gate electrode fills the channel recess and crosses the active region in the second direction. A gate insulating layer is interposed between the gate electrode and the active region.

    摘要翻译: 金属氧化物半导体(MOS)包括设置在半导体衬底中以限定有源区的隔离层。 源极区域和漏极区域设置在有源区域的两侧,使得从源极区域到漏极区域限定第一方向。 通道凹槽设置在源区和漏区之间的有源区中。 当从沿着与第一方向正交的第二方向截取的横截面视图观察时,通道凹部具有凸形表面。 栅电极填充通道凹槽并沿第二方向跨过有源区。 栅极绝缘层插入在栅电极和有源区之间。

    Fabrication of local damascene finFETs using contact type nitride damascene mask
    14.
    发明申请
    Fabrication of local damascene finFETs using contact type nitride damascene mask 失效
    使用接触式氮化物镶嵌掩模制造局部大马士革finFET

    公开(公告)号:US20090121292A1

    公开(公告)日:2009-05-14

    申请号:US12318238

    申请日:2008-12-23

    IPC分类号: H01L29/78

    摘要: Disclosed are methods for forming FinFETs using a first hard mask pattern to define active regions and a second hard mask to protect portions of the insulating regions between active regions. The resulting field insulating structure has three distinct regions distinguished by the vertical offset from a reference plane defined by the surface of the active regions. These three regions will include a lower surface found in the recessed openings resulting from the damascene etch, an intermediate surface and an upper surface on the remaining portions of the lateral field insulating regions. The general correspondence between the reference plane and the intermediate surface will tend to suppress or eliminate residual gate electrode materials from this region during formation of the gate electrodes, thereby improving the electrical isolation between adjacent active regions and improving the performance of the resulting semiconductor devices.

    摘要翻译: 公开了使用第一硬掩模图案形成FinFET以限定有源区的方法和用于保护有源区之间绝缘区的部分的第二硬掩模的方法。 所得到的场绝缘结构具有由与活性区域的表面限定的参考平面的垂直偏移区分的三个不同区域。 这三个区域将包括由镶嵌蚀刻产生的凹入开口中的下表面,侧面场绝缘区域的其余部分上的中间表面和上表面。 在形成栅电极期间,参考平面和中间表面之间的一般对应关系将倾向于抑制或消除该区域中的剩余栅电极材料,从而改善相邻有源区之间的电隔离并提高所得半导体器件的性能。

    SYSTEM AND METHOD OF CHECKING INTEGRITY OF CONTENT AND METADATA
    15.
    发明申请
    SYSTEM AND METHOD OF CHECKING INTEGRITY OF CONTENT AND METADATA 审中-公开
    检查内容和元数据的完整性的系统和方法

    公开(公告)号:US20080313198A1

    公开(公告)日:2008-12-18

    申请号:US12029799

    申请日:2008-02-12

    IPC分类号: G06F17/30

    CPC分类号: G06F16/178 G06F16/2358

    摘要: A system and method of checking the integrity of content and metadata are provided. The integrity-checking method includes storing changed content in a first storage space, and storing the metadata corresponding to the changed content in a second storage space.

    摘要翻译: 提供了检查内容和元数据的完整性的系统和方法。 完整性检查方法包括将改变的内容存储在第一存储空间中,并且将与改变的内容相对应的元数据存储在第二存储空间中。

    Method for abstracting histogram of HSV color
    16.
    发明授权
    Method for abstracting histogram of HSV color 有权
    提取HSV色彩直方图的方法

    公开(公告)号:US07447352B2

    公开(公告)日:2008-11-04

    申请号:US10514528

    申请日:2002-05-20

    申请人: Yong Sung Kim

    发明人: Yong Sung Kim

    CPC分类号: H04N1/644 G06T7/90

    摘要: A method Abstract a histogram of HSV (Hue-Saturation-Value) colors from a color signal. The method includes receiving the color signal having a luminance component (Y) and chrominance components (CbCr). One section of a lookup table is selected according to the luminance component (Y) of the received color signal. The lookup table is divided into a plurality of sections each storing quantizing index values. Each section is divided by concentric circles corresponding to quantizing boundaries of the Saturation from a center, and divided by radial lines. Corresponding quantizing index values are selected according to the chrominance components (CbCr) of the received color signal in the selected section. The histogram index of the HSV colors is abstracted with reference to the selected section and the quantizing index values selected in the selected section.

    摘要翻译: 一种方法从颜色信号中抽取HSV(色相饱和度值)颜色的直方图。 该方法包括接收具有亮度分量(Y)和色度分量(CbCr)的彩色信号。 根据所接收的颜色信号的亮度分量(Y)来选择查找表的一个部分。 查找表被分成多个部分,每个部分存储量化索引值。 每个部分由对应于饱和度从中心的量化边界的同心圆除以径向线除。 根据所选择的部分中所接收的颜色信号的色度分量(CbCr)来选择相应的量化指标值。 参考所选部分和在所选部分中选择的量化指标值,抽取HSV颜色的直方图索引。

    Fabrication of layer-by-layer photonic crystals using two polymer microtransfer molding
    17.
    发明申请
    Fabrication of layer-by-layer photonic crystals using two polymer microtransfer molding 失效
    使用两个聚合物微转移模塑制造逐层光子晶体

    公开(公告)号:US20070289119A1

    公开(公告)日:2007-12-20

    申请号:US11455486

    申请日:2006-06-19

    摘要: A method of manufacturing photonic band gap structures operable in the optical spectrum has been presented. The method comprises the steps of filling a plurality of grooves of an elastomeric mold with a UV curable first polymer, each groove in parallel with each other and partially curing the first polymer. A second polymer is coated on the first polymer. A substrate or a multi-layer polymer structure is placed on the filled mold and the resulting structure is exposed to UV light (i.e., is UV cured). The mold is peeled away from the first and second polymers such that a layer of polymer rods is formed on the substrate/multi-layer polymer structure. The process is repeated until a desired number of layers have been formed. The multi-layer structure can be used to create ceramic and metallic photonic band gaps by infiltration, electro-deposition, and/or metal coating.

    摘要翻译: 已经提出了在光谱中可操作的制造光子带隙结构的方法。 该方法包括以下步骤:用UV可固化的第一聚合物填充弹性体模具的多个凹槽,每个凹槽彼此平行并部分固化第一聚合物。 将第二聚合物涂覆在第一聚合物上。 将基底或多层聚合物结构放置在填充的模具上,并将所得结构暴露于UV光(即,UV固化)。 将模具从第一和第二聚合物剥离,使得在基底/多层聚合物结构上形成聚合物棒层。 重复该过程,直到形成所需数量的层。 多层结构可用于通过渗透,电沉积和/或金属涂层来产生陶瓷和金属光子带隙。

    Apparatus and method of managing storage space through time-variant consumption estimation
    19.
    发明申请
    Apparatus and method of managing storage space through time-variant consumption estimation 有权
    通过时变消费估计来管理存储空间的装置和方法

    公开(公告)号:US20070186064A1

    公开(公告)日:2007-08-09

    申请号:US11653900

    申请日:2007-01-17

    IPC分类号: G06F13/00

    摘要: An apparatus and a method for managing a storage space through time-variant consumption estimation. More particularly, an apparatus and a method for managing a storage space through time-variant consumption estimation that estimates consumption of an entire storage space when a user instructs program editing, program recording or reserved recording, and so on. When there is a possibility that the estimated consumption exceeds a predetermined value, immediately providing a user with information indicating that the storage space is lacking. The apparatus includes a storage unit storing contents in the storage space, a consumption estimation unit estimating time-variant consumption of the storage space, a contents management unit deleting at least a portion of the contents or storing at least a portion of additionally input contents according to the estimation result, and an output unit outputting the deletion or storage result.

    摘要翻译: 一种通过时变消费估计来管理存储空间的装置和方法。 更具体地说,一种用于通过时变消耗估计来管理存储空间的装置和方法,其估计当用户指示程序编辑,程序记录或预约记录时整个存储空间的消耗。 当估计消耗有可能超过预定值时,立即向用户提供指示存储空间不足的信息。 该装置包括:存储单元,存储在存储空间中的内容;消耗估计单元,估计存储空间的时变消耗;内容管理单元,删除至少一部分内容,或者存储至少一部分附加输入内容; 以及输出单元输出删除或存储结果。

    Fabrication of local damascene finFETs using contact type nitride damascene mask
    20.
    发明申请
    Fabrication of local damascene finFETs using contact type nitride damascene mask 失效
    使用接触式氮化物镶嵌掩模制造局部大马士革finFET

    公开(公告)号:US20070111455A1

    公开(公告)日:2007-05-17

    申请号:US11508992

    申请日:2006-08-24

    IPC分类号: H01L21/84 H01L21/336

    摘要: Disclosed are methods for forming FinFETs using a first hard mask pattern to define active regions and a second hard mask to protect portions of the insulating regions between active regions. The resulting field insulating structure has three distinct regions distinguished by the vertical offset from a reference plane defined by the surface of the active regions. These three regions will include a lower surface found in the recessed openings resulting from the damascene etch, an intermediate surface and an upper surface on the remaining portions of the lateral field insulating regions. The general correspondence between the reference plane and the intermediate surface will tend to suppress or eliminate residual gate electrode materials from this region during formation of the gate electrodes, thereby improving the electrical isolation between adjacent active regions and improving the performance of the resulting semiconductor devices.

    摘要翻译: 公开了使用第一硬掩模图案形成FinFET以限定有源区的方法和用于保护有源区之间绝缘区的部分的第二硬掩模的方法。 所得到的场绝缘结构具有由与活性区域的表面限定的参考平面的垂直偏移区分的三个不同区域。 这三个区域将包括由镶嵌蚀刻产生的凹入开口中的下表面,侧面场绝缘区域的其余部分上的中间表面和上表面。 在形成栅电极期间,参考平面和中间表面之间的一般对应关系将倾向于抑制或消除该区域中的剩余栅电极材料,从而改善相邻有源区之间的电隔离并提高所得半导体器件的性能。