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    Fabrication of layer-by-layer photonic crystals using two polymer microtransfer molding
    1.
    发明授权
    Fabrication of layer-by-layer photonic crystals using two polymer microtransfer molding 失效
    使用两个聚合物微转移模塑制造逐层光子晶体

    公开(公告)号：US07625515B2

    公开(公告)日：2009-12-01

    申请号：US11455486

    申请日：2006-06-19

    申请人： Jae-Hwang Lee ,  Kai-Ming Ho ,  Yong-Sung Kim ,  Kristen Constant ,  Chang-Hwan Kim

    发明人： Jae-Hwang Lee ,  Kai-Ming Ho ,  Yong-Sung Kim ,  Kristen Constant ,  Chang-Hwan Kim

    IPC分类号： H01L21/00

    CPC分类号： B29C41/36 ,  B29C33/42 ,  B29C39/025 ,  B29C39/026 ,  B29C41/22 ,  B82Y20/00 ,  G02B6/1225 ,  G02B6/138 ,  Y10T29/49002

    摘要： A method of manufacturing photonic band gap structures operable in the optical spectrum has been presented. The method comprises the steps of filling a plurality of grooves of an elastomeric mold with a UV curable first polymer, each groove in parallel with each other and partially curing the first polymer. A second polymer is coated on the first polymer. A substrate or a multi-layer polymer structure is placed on the filled mold and the resulting structure is exposed to UV light (i.e., is UV cured). The mold is peeled away from the first and second polymers such that a layer of polymer rods is formed on the substrate/multi-layer polymer structure. The process is repeated until a desired number of layers have been formed. The multi-layer structure can be used to create ceramic and metallic photonic band gaps by infiltration, electro-deposition, and/or metal coating.

    摘要翻译： 已经提出了在光谱中可操作的制造光子带隙结构的方法。 该方法包括以下步骤：用UV可固化的第一聚合物填充弹性体模具的多个凹槽，每个凹槽彼此平行并部分固化第一聚合物。 将第二聚合物涂覆在第一聚合物上。 将基底或多层聚合物结构放置在填充的模具上，并将所得结构暴露于UV光（即，UV固化）。 将模具从第一和第二聚合物剥离，使得在基底/多层聚合物结构上形成聚合物棒层。 重复该过程，直到形成所需数量的层。 多层结构可用于通过渗透，电沉积和/或金属涂层来产生陶瓷和金属光子带隙。

    Fabrication of layer-by-layer photonic crystals using two polymer microtransfer molding
    2.
    发明申请
    Fabrication of layer-by-layer photonic crystals using two polymer microtransfer molding 失效
    使用两个聚合物微转移模塑制造逐层光子晶体

    公开(公告)号：US20070289119A1

    公开(公告)日：2007-12-20

    申请号：US11455486

    申请日：2006-06-19

    申请人： Jae-Hwang Lee ,  Kai-Ming Ho ,  Yong-Sung Kim ,  Kristen Constant ,  Chang-Hwan Kim

    发明人： Jae-Hwang Lee ,  Kai-Ming Ho ,  Yong-Sung Kim ,  Kristen Constant ,  Chang-Hwan Kim

    IPC分类号： H01S4/00 ,  C23C14/00 ,  C07K1/26 ,  B29C35/08 ,  B29C41/22

    CPC分类号： B29C41/36 ,  B29C33/42 ,  B29C39/025 ,  B29C39/026 ,  B29C41/22 ,  B82Y20/00 ,  G02B6/1225 ,  G02B6/138 ,  Y10T29/49002

    摘要： A method of manufacturing photonic band gap structures operable in the optical spectrum has been presented. The method comprises the steps of filling a plurality of grooves of an elastomeric mold with a UV curable first polymer, each groove in parallel with each other and partially curing the first polymer. A second polymer is coated on the first polymer. A substrate or a multi-layer polymer structure is placed on the filled mold and the resulting structure is exposed to UV light (i.e., is UV cured). The mold is peeled away from the first and second polymers such that a layer of polymer rods is formed on the substrate/multi-layer polymer structure. The process is repeated until a desired number of layers have been formed. The multi-layer structure can be used to create ceramic and metallic photonic band gaps by infiltration, electro-deposition, and/or metal coating.

    摘要翻译： 已经提出了在光谱中可操作的制造光子带隙结构的方法。 该方法包括以下步骤：用UV可固化的第一聚合物填充弹性体模具的多个凹槽，每个凹槽彼此平行并部分固化第一聚合物。 将第二聚合物涂覆在第一聚合物上。 将基底或多层聚合物结构放置在填充的模具上，并将所得结构暴露于UV光（即，UV固化）。 将模具从第一和第二聚合物剥离，使得在基底/多层聚合物结构上形成聚合物棒层。 重复该过程，直到形成所需数量的层。 多层结构可用于通过渗透，电沉积和/或金属涂层来产生陶瓷和金属光子带隙。

    Protein scaffold library based on kringle domain structure and uses thereof
    4.
    发明授权
    Protein scaffold library based on kringle domain structure and uses thereof 有权
    基于kringle结构域的蛋白质支架库及其用途

    公开(公告)号：US08492343B2

    公开(公告)日：2013-07-23

    申请号：US13058810

    申请日：2009-08-07

    申请人： Yong-Sung Kim ,  Myung-Hee Kwon ,  Chang-Han Lee

    发明人： Yong-Sung Kim ,  Myung-Hee Kwon ,  Chang-Han Lee

    IPC分类号： A61K38/00 ,  A61P35/00 ,  C12Q1/68 ,  C12N15/74 ,  C12N1/20

    CPC分类号： C12N15/1044 ,  C40B40/10

    摘要： There are provided a Kringle domain structure, comprising: inducing artificial mutations at amino acid residues except for conserved amino acid residues that are important to maintain the structural scaffold of a Kringle domain; and protein scaffold variants, based on the Kringle domain structure, which modulate the biological activities of a variety of target molecules derived from the protein scaffold library by specifically binding to the target molecules. Also, there is provided a method for constructing homo-/hetero-oligomers which allow multi-specificity binding to multiple targets by the tandem assembly monomeric Kringle domain variants using a linker. Additionally, there is provided a method for preparing multispecific monomers and multivalent monomers by grafting target-binding loops of a Kringle domain variant into non-binding loops of another Kringle domain variant with the same or different target binding specificity. Furthermore, a protein scaffold variant based on the Kringle domain structure that specifically binds to target molecules, DNA encoding the protein scaffold variant, or a method and composition for prevention, detection, diagnosis, treatment or relieving diseases or disorders, particularly cancers and other immune-related diseases, comprising: administering an effective amount of the related molecule to animals, preferably human.

    摘要翻译： 提供了一种Kringle结构域结构，其包括：除了保持Kringle结构域的结构支架重要的保守氨基酸残基之外，在氨基酸残基处诱导人工突变; 和蛋白质支架变体，其基于Kringle结构域结构，其通过特异性结合靶分子来调节衍生自蛋白质支架文库的各种靶分子的生物学活性。 此外，提供了一种构建同 - 异寡聚物的方法，其允许使用接头通过串联组装单体Kringle结构域变体多特异性结合多个靶标。 另外，提供了通过将Kringle结构域变体的靶结合环转移到具有相同或不同靶结合特异性的另一个Kringle结构域变体的非结合环中来制备多特异性单体和多价单体的方法。 此外，基于特异性结合靶分子的Kringle结构域结构的蛋白质支架变体，编码蛋白质支架变体的DNA，或用于预防，检测，诊断，治疗或缓解疾病或病症，特别是癌症和其他免疫的方法和组合物 相关疾病，包括：向动物，优选人类施用有效量的相关分子。

    Metal oxide semiconductor (MOS) transistors having a recessed gate electrode
    5.
    发明授权
    Metal oxide semiconductor (MOS) transistors having a recessed gate electrode 有权
    具有凹陷栅电极的金属氧化物半导体（MOS）晶体管

    公开(公告)号：US08487352B2

    公开(公告)日：2013-07-16

    申请号：US13236389

    申请日：2011-09-19

    申请人： Yong-Sung Kim ,  Tae-Young Chung

    发明人： Yong-Sung Kim ,  Tae-Young Chung

    IPC分类号： H01L27/148

    CPC分类号： H01L29/7834 ,  H01L29/51 ,  H01L29/66621

    摘要： A metal oxide semiconductor (MOS) includes an isolation layer disposed in a semiconductor substrate to define an active region. A source region and a drain region are disposed on both sides of the active region such that a first direction is defined from the source region to the drain region. A channel recess is disposed in the active region between the source and drain regions. The channel recess has a convex surface when viewed from a cross-sectional view taken along a second direction orthogonal to the first direction. A gate electrode fills the channel recess and crosses the active region in the second direction. A gate insulating layer is interposed between the gate electrode and the active region.

    摘要翻译： 金属氧化物半导体（MOS）包括设置在半导体衬底中以限定有源区的隔离层。 源极区域和漏极区域设置在有源区域的两侧，使得从源极区域到漏极区域限定第一方向。 通道凹槽设置在源区和漏区之间的有源区中。 当从沿着与第一方向正交的第二方向截取的横截面视图观察时，通道凹部具有凸形表面。 栅电极填充通道凹槽并沿第二方向跨过有源区。 栅极绝缘层插入在栅电极和有源区之间。

    Fabrication of local damascene finFETs using contact type nitride damascene mask
    7.
    发明授权
    Fabrication of local damascene finFETs using contact type nitride damascene mask 失效

    公开(公告)号：US07488654B2

    公开(公告)日：2009-02-10

    申请号：US11508992

    申请日：2006-08-24

    申请人： Yong-Sung Kim ,  Tae-Young Chung

    发明人： Yong-Sung Kim ,  Tae-Young Chung

    IPC分类号： H01L21/336

    CPC分类号： H01L29/785 ,  H01L27/1211 ,  H01L29/66795

    摘要： Disclosed are methods for forming FinFETs using a first hard mask pattern to define active regions and a second hard mask to protect portions of the insulating regions between active regions. The resulting field insulating structure has three distinct regions distinguished by the vertical offset from a reference plane defined by the surface of the active regions. These three regions will include a lower surface found in the recessed openings resulting from the damascene etch, an intermediate surface and an upper surface on the remaining portions of the lateral field insulating regions. The general correspondence between the reference plane and the intermediate surface will tend to suppress or eliminate residual gate electrode materials from this region during formation of the gate electrodes, thereby improving the electrical isolation between adjacent active regions and improving the performance of the resulting semiconductor devices.

    Method of fabricating gate of fin type transistor
    8.
    发明授权
    Method of fabricating gate of fin type transistor 有权
    鳍型晶体管栅极的制造方法

    公开(公告)号：US07413943B2

    公开(公告)日：2008-08-19

    申请号：US11460905

    申请日：2006-07-28

    申请人： Yong-Sung Kim ,  Tae-Young Chung ,  Soo-Ho Shin

    发明人： Yong-Sung Kim ,  Tae-Young Chung ,  Soo-Ho Shin

    IPC分类号： H01L21/336 ,  H01L31/062

    CPC分类号： H01L21/823437 ,  H01L21/823412 ,  H01L29/66795 ,  H01L29/7851

    摘要： A method of fabricating a gate of a fin type transistor includes forming hard masks to define active regions of a substrate. A shallow trench isolation method is performed to form a first device separation layer, and then an etch-back process is performed such that the active regions protrude. Sidewall protection layers are formed on sidewalls of the active region, and a second device separation layer is formed thereon, thereby obtaining a device isolation region. The sidewall protection layers include an insulation material with an etch selectivity with respect to an insulation material composing the device isolation region. The device isolation region is selectively etched to form recesses for a fin type active region. Dry etching and wet etching are performed on the silicon nitride to remove the hard masks and the sidewall protection layers, respectively. Gates are formed to fill the recesses.

    摘要翻译： 制造鳍式晶体管的栅极的方法包括形成硬掩模以限定衬底的有源区。 执行浅沟槽隔离方法以形成第一器件分离层，然后执行回蚀处理，使得有源区域突出。 侧壁保护层形成在有源区的侧壁上，并且在其上形成第二器件分离层，从而获得器件隔离区。 侧壁保护层包括相对于构成器件隔离区域的绝缘材料具有蚀刻选择性的绝缘材料。 选择性地蚀刻器件隔离区以形成翅片型有源区的凹槽。 对氮化硅进行干蚀刻和湿蚀刻以分别去除硬掩模和侧壁保护层。 形成门以填充凹部。

    SEMICONDUCTOR DEVICE HAVING VERTICAL CHANNELS AND METHOD OF MANUFACTURING THE SAME
    10.
    发明申请
    SEMICONDUCTOR DEVICE HAVING VERTICAL CHANNELS AND METHOD OF MANUFACTURING THE SAME 审中-公开
    具有垂直通道的半导体器件及其制造方法

    公开(公告)号：US20140103482A1

    公开(公告)日：2014-04-17

    申请号：US14109517

    申请日：2013-12-17

    申请人： Yong-Sung Kim ,  Tae-Young CHUNG ,  Soo-Ho SHIN

    发明人： Yong-Sung Kim ,  Tae-Young CHUNG ,  Soo-Ho SHIN

    IPC分类号： H01L29/06 ,  H01L27/088

    CPC分类号： H01L21/28123 ,  H01L21/76224 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/10826 ,  H01L27/10879 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/4238 ,  H01L29/66795 ,  H01L29/7802 ,  H01L29/7827 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/7853

    摘要： A method of manufacturing a semiconductor device which can prevent leakage current caused by gate electrodes intersecting element isolation layers in a major axis of an active region, and which further has vertical channels to provide a sufficient overlap margin, and a semiconductor device manufactured using the above method. The device includes gate electrodes formed on element isolation layers that are disposed between active regions and have top surfaces that are higher than the top surfaces of the active regions. Since the gate electrodes are formed on the element isolation layers, leakage current in a semiconductor substrate is prevented. In addition, the gate electrodes are formed using a striped shape mask pattern, thereby obtaining a sufficient overlap margin compared to a contact shape or bar shape pattern.

    摘要翻译： 一种制造半导体器件的方法，该半导体器件能够防止由有源区的长轴与元件隔离层相交的栅电极引起的泄漏电流，并且还具有垂直沟道以提供足够的重叠余量;以及使用上述制造的半导体器件 方法。 该器件包括形成在元件隔离层上的栅电极，它们设置在有源区之间并具有高于有源区顶表面的顶表面。 由于栅电极形成在元件隔离层上，所以防止了半导体衬底中的漏电流。 此外，使用条纹形掩模图案形成栅电极，从而与接触形状或条形图案相比获得足够的重叠余量。