公开(公告)号：US20240071985A1

公开(公告)日：2024-02-29

申请号：US17896746

申请日：2022-08-26

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： RAHUL AGARWAL ,  CHANDRA SEKHAR MANDALAPU ,  RAJA SWAMINATHAN

IPC: H01L23/00 ,  H01L25/065

CPC classification number: H01L24/80 ,  H01L24/08 ,  H01L25/0657 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2924/381

Abstract: A method for forming a semiconductor assembly that includes forming a first set of layers on a first wafer, where one or more layers of the first set includes one or more devices of the semiconductor assembly. The method further includes forming a second set of layers on a second wafer, where one or more layers of the second set include connections between one or more of the devices of the semiconductor assembly. The method additionally includes coupling a layer of the first set to a layer of the second set using metal to metal hybrid bonding.

公开(公告)号：US20240071903A1

公开(公告)日：2024-02-29

申请号：US17896616

申请日：2022-08-26

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： GABRIEL H. LOH ,  RAJA SWAMINATHAN ,  RAHUL AGARWAL

IPC: H01L23/522 ,  H01L23/16 ,  H01L23/528

CPC classification number: H01L23/5226 ,  H01L23/16 ,  H01L23/528

Abstract: A semiconductor package assembly includes a die having a front surface and a back surface opposite to and parallel to the front surface. A first portion of a front surface of an interconnect die is coupled to a portion of the back surface of the die. The interconnect die includes a connectivity region that is coupled to one or more through-die vias in the die through the back surface of the die. A spacer component is coupled to a second portion of the front surface of the interconnect die. The spacer component includes conductive connections, with one or more of the conductive connections are coupled to the conductive pathways of the connectivity region of the interconnect die.

公开(公告)号：US20240019649A1

公开(公告)日：2024-01-18

申请号：US18357376

申请日：2023-07-24

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： BRETT P. WILKERSON ,  RAJA SWAMINATHAN ,  KONG TOON NG ,  RAHUL AGARWAL

IPC: G02B6/42

CPC classification number: G02B6/4274 ,  G02B6/4255 ,  G02B6/425 ,  G02B6/43

Abstract: A semiconductor package includes a first mold layer at least partially encasing at least one photonic integrated circuit. A redistribution layer structure is fabricated on the first mold layer, the redistribution layer structure including dielectric material and conductive structures. A second mold layer at least partially encasing at least one semiconductor chip is fabricated on the redistribution layer structure. The redistribution layer structure provides electrical pathways between the at least one semiconductor chip and the at least one photonic integrated circuit. One or more voids are defined in the second mold layer in an area above an optical interface of the at least one photonic integrated circuit such that light is transmittable through dielectric material above the optical interface.

公开(公告)号：US20230201952A1

公开(公告)日：2023-06-29

申请号：US17563830

申请日：2021-12-28

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： PRIYAL SHAH ,  RAHUL AGARWAL ,  RAJA SWAMINATHAN ,  BRETT P. WILKERSON

IPC: B23K20/02 ,  B23K20/24

CPC classification number: B23K20/02 ,  B23K20/24 ,  B23K2101/40

Abstract: A semiconductor device includes a first die, the first die including a first dielectric layer and a plurality of first bond pads formed within apertures in the first dielectric layer, and a second die bonded to the first die, the second die including a second dielectric layer and a plurality of second bond pads protruding from the second dielectric layer. The first die is bonded to the second die such that the plurality of second bond pads protrude into the apertures in the first dielectric layer to establish respective metallurgical bonds with the plurality of first bond pads. A reduction in the distance between the respective bond pads of the dies results in a lower temperature for establishing a hybrid bond.

公开(公告)号：US20230197563A1

公开(公告)日：2023-06-22

申请号：US17554968

申请日：2021-12-17

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： RAHUL AGARWAL ,  RAJA SWAMINATHAN

IPC: H01L23/427 ,  H01L27/108

CPC classification number: H01L23/427 ,  H01L27/10897

Abstract: In an implementation, a semiconductor chip device includes a first semiconductor chip that includes a first portion and a second portion. The first portion can be a higher heat producing portion and the second portion can be a lower heat producing portion. A second semiconductor chip is stacked on the first semiconductor chip over the second portion. A dummy component is stacked on the first semiconductor chip over the first portion. The dummy component includes a plurality of thermal pipes providing a thermal path from a first surface of the dummy component to an opposite second surface of the dummy component.