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    WIDEBAND QUADRATURE ERROR DETECTION AND CORRECTION
    11.
    发明申请
    WIDEBAND QUADRATURE ERROR DETECTION AND CORRECTION 审中-公开
    宽带错误检测和校正

    公开(公告)号：US20150030103A1

    公开(公告)日：2015-01-29

    申请号：US14340461

    申请日：2014-07-24

    Applicant: Analog Devices, Inc.

    Inventor： Raju Hormis ,  Steven R. Bal ,  Antonio Montalvo ,  David J. McLaurin ,  Martin McCormick

    IPC: H04L1/24 ,  H04L27/36

    Abstract: A transmission module is provided that includes a transmitter, a loopback receiver, and a QEC controller. The QEC controller identifies quadrature imbalance in the transmitter based at least one a comparison of the data signals at the output of the loopback receiver with data signals at the input of the transmitter. Based on the comparison, the QEC controller can adjust one or more characteristics of the transmitter to correct quadrature errors in the transmitter.

    Abstract translation: 提供了一种传输模块，其包括发射机，环回接收机和QEC控制器。 QEC控制器通过至少一个环回接收机输出端的数据信号与发射机输入端的数据信号进行比较，来识别发射机的正交不平衡。 基于比较，QEC控制器可以调整发射机的一个或多个特性来校正发射机的正交误差。

    SYSTEM AND METHOD TO CALIBRATE THE FREQUENCY RESPONSE OF AN ELECTRONIC FILTER
    12.
    发明申请
    SYSTEM AND METHOD TO CALIBRATE THE FREQUENCY RESPONSE OF AN ELECTRONIC FILTER 有权
    校准电子滤波器频率响应的系统和方法

    公开(公告)号：US20140105264A1

    公开(公告)日：2014-04-17

    申请号：US13650707

    申请日：2012-10-12

    Applicant: ANALOG DEVICES, INC.

    Inventor： David J. McLaurin ,  Christopher Mayer

    IPC: H04B17/00

    CPC classification number: H04B17/11

    Abstract: A system and method provide for calibrating the frequency response of an electronic filter. The system and method include a radio transmitter with both in-phase and quadrature baseband paths. Each baseband path includes a numerically controlled oscillator (“NCO”), a digital signal path, a digital-to-analog converter (“DAC”), and an analog filter. A low frequency tone is applied from the NCO from one of the baseband path, while a high frequency tone is applied from the NCO in the other baseband path. An analog peak detector at output determines which analog filter has the largest amplitude at the output. The peak detector offset between the two analog filters is offset by stimulating the in-phase and quadrature baseband paths with the respective NCOs to find an amplitude difference between the output signals from the NCOs that makes the output of the analog filters the same. Calibration is then performed on the corner frequency and filter peaking through respective stimulation of the in-phase and quadrature baseband paths. The system and method is advantageous as it allows for very accurate calibration of both the filter corner frequency and peaking during a standard transmission operating mode with little additional hardware required.

    Abstract translation: 一种用于校准电子滤波器的频率响应的系统和方法。 该系统和方法包括具有同相和正交基带路径的无线电发射机。 每个基带路径包括数控振荡器（“NCO”），数字信号路径，数模转换器（“DAC”）和模拟滤波器。 来自基带路径之一的NCO施加低频音调，而在另一个基带路径中从NCO施加高频音调。 输出端的模拟峰值检测器决定了哪个模拟滤波器在输出端具有最大幅度。 两个模拟滤波器之间的峰值检测器偏移通过用相应的NCO刺激同相和正交基带路径来偏移，以在来自NCO的输出信号之间找到使模拟滤波器的输出相同的振幅差。 然后在角频率上进行校准，并通过相位和正交基带路径的相应刺激来过滤峰值。 该系统和方法是有利的，因为它允许在标准传输操作模式期间非常精确地校准滤波器转角频率和峰值，同时需要少量额外的硬件。

    VARIABLE GAIN AMPLIFIERS WITH FINE ATTENUATION STEP CONTROL AND FLAT SIGNAL-TO-NOISE RATIO VERSUS ATTENUATION
    13.
    发明申请
    VARIABLE GAIN AMPLIFIERS WITH FINE ATTENUATION STEP CONTROL AND FLAT SIGNAL-TO-NOISE RATIO VERSUS ATTENUATION 有权

    公开(公告)号：US20240421780A1

    公开(公告)日：2024-12-19

    申请号：US18335459

    申请日：2023-06-15

    Applicant: Analog Devices, Inc.

    Inventor： David J. McLaurin ,  Kevin Gard

    IPC: H03F3/195 ,  H03F1/56 ,  H03G1/00 ,  H03G3/30

    Abstract: Variable gain amplifiers (VGAs) with fine attenuation step control and flat signal-to-noise ratio (SNR) versus attenuation are provided. In certain embodiments, a VGA includes an input that receives a radio frequency (RF) input signal, a segmented amplification circuit including multiple amplification cells that operate in parallel to amplify the RF input signal to generate multiple amplified RF signals, an impedance ladder including multiple taps each connected to a different node of the impedance ladder, and switches that control routing of the amplified RF signals to one or more selected taps of the impedance ladder. Accordingly, the VGA uses the switches to connect the outputs of the segmented amplification circuit to the selected tap(s) of the impedance ladder. By changing the tap selection, the attenuation step of the VGA is controlled.

    Apparatus and methods for phase synchronization of phase-locked loops
    14.
    发明授权
    Apparatus and methods for phase synchronization of phase-locked loops 有权

    公开(公告)号：US10659065B2

    公开(公告)日：2020-05-19

    申请号：US15957766

    申请日：2018-04-19

    Applicant: Analog Devices, Inc.

    Inventor： Christopher Mayer ,  David J. McLaurin ,  Christopher W. Angell ,  Sudhir Desai ,  Steven R. Bal

    IPC: H03L7/197 ,  H03L7/087 ,  H03L7/23 ,  H03L7/089 ,  H03L7/091 ,  H03L7/093 ,  H04B7/0413 ,  H04L7/033

    Abstract: Apparatus and methods for phase synchronization of phase-locked loops (PLLs) are provided. In certain configurations, an RF communication system includes a PLL that generates one or more output clock signals and a phase synchronization circuit that synchronizes a phase of the PLL. The phase synchronization circuit includes a sampling circuit that generates samples by sampling the one or more output clock signals based on timing of a reference clock signal. Additionally, the phase synchronization circuit includes a phase difference calculation circuit that generates a phase difference signal based on the samples and a tracking digital phase signal representing the phase of the PLL. The phase synchronization circuit further includes a phase adjustment control circuit that provides a phase adjustment to the PLL based on the phase difference signal so as to synchronize the PLL.

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