公开(公告)号：US20240036680A1

公开(公告)日：2024-02-01

申请号：US18323659

申请日：2023-05-25

Applicant: Apple Inc.

Inventor： Shinya Ono ,  Suhwan Moon ,  Dong-Gwang Ha ,  Jiaxi Hu ,  Hao-Lin Chiu ,  Kwang Soon Park ,  Hassan Edrees ,  Wen-I Hsieh ,  Jiun-Jye Chang ,  Chin-Wei Lin ,  Kyung Wook Kim

IPC: G06F3/041 ,  G09G3/3208 ,  G06F3/044

CPC classification number: G06F3/04184 ,  G06F3/0412 ,  G09G3/3208 ,  G06F3/0446 ,  G06F3/0444 ,  G06F2203/04107 ,  G06F2203/04112

Abstract: An electronic device may have a display with touch sensors. One or more shielding layers may be interposed between the display and the touch sensors. The display may include transistors with gate conductors, a first planarization layer formed over the gate conductors, one or more contacts formed in a first source-drain layer within the first planarization layer, a second planarization layer formed on the first planarization layer, one or more data lines formed in a second source-drain layer within the second planarization layer, a third planarization layer formed on the second planarization layer, and a data line shielding structure formed at least partly in a third source-drain layer within the third planarization layer. The data line shielding structure may be a routing line, a blanket layer, a mesh layer formed in one or more metal layers, and/or a data line covering another data line.

公开(公告)号：US20230014107A1

公开(公告)日：2023-01-19

申请号：US17749045

申请日：2022-05-19

Applicant: Apple Inc.

Inventor： Rungrot Kitsomboonloha ,  Chin-Wei Lin ,  Shinya Ono ,  Gihoon Choo ,  Hao-Lin Chiu ,  Kyung Wook Kim ,  Pei-En Chang ,  Szu-Hsien Lee ,  Zino Lee

IPC: G09G3/3225

Abstract: A display may include an array of pixels that receive control signals from a chain of gate drivers. Each gate driver may include a logic sub-circuit and an output buffer sub-circuit. The output buffer sub-circuit may include depletion mode semiconducting oxide transistors with high mobility. The logic sub-circuit may include semiconducting oxide transistors, some of which can be depletion mode transistors and some of which can be enhancement mode transistors with lower mobility. The logic sub-circuit may include at least a carry circuit, a voltage setting circuit, an inverting circuit, a discharge circuit.

公开(公告)号：US10754212B2

公开(公告)日：2020-08-25

申请号：US16041667

申请日：2018-07-20

Applicant: Apple Inc.

Inventor： Byung Duk Yang ,  Hao-Lin Chiu ,  Kwang Soon Park ,  Kyung Wook Kim ,  Sai-Chang Liu ,  Shih Chang Chang

IPC: G02F1/1335 ,  G02F1/1362 ,  G02F1/1368 ,  G02F1/1333

Abstract: A display may have pixels configured to display images. The pixels may be formed from thin-film transistor circuitry on a substrate. Color filter elements formed from colored polymer such as colored photoimageable polymer may be formed on the substrate. A black matrix formed from black photoimageable polymer may have an array of openings. The colored polymer may have first portions that overlap the black matrix and second portions in the openings that form the color filter elements. In some portions of the pixels, the thin-film transistor circuitry may be interposed between the first portions of the colored polymer and the black matrix. In other portions of the pixels, data lines may be formed that are overlapped by the black matrix and that are interposed between the first portions of the colored polymer and the black matrix.

公开(公告)号：US20170061837A1

公开(公告)日：2017-03-02

申请号：US14995796

申请日：2016-01-14

Applicant: APPLE INC.

Inventor： Howard H. Tang ,  Wei Chen ,  Paolo Sacchetto ,  Chaohao Wang ,  Chun-Yao Huang ,  Hao-Lin Chiu

IPC: G09G3/00

CPC classification number: G09G3/00 ,  G09G3/20 ,  G09G2300/0426 ,  G09G2310/0218 ,  G09G2310/0278 ,  G09G2310/0281 ,  G09G2320/0209 ,  G09G2320/0219

Abstract: A display device may include a plurality of pixels, a plurality of source lines that may provide a plurality of data line signals to the plurality of pixels, a plurality of gate lines that may provide a plurality of gate signals to a plurality of switches associated with the plurality of pixels, and a plurality of voltage gate lines disposed parallel to the plurality of source lines and coupled to the plurality of gate lines at a plurality of cross point nodes. The plurality of cross point nodes are positioned in a pseudo random order across the display device.

Abstract translation: 显示装置可以包括多个像素，可以向多个像素提供多条数据线信号的多条源极线，可以向与多个像素相关联的多个开关提供多个栅极信号的多条栅极线 所述多个像素以及与所述多个源极线平行设置并且在多个交叉点节点处耦合到所述多个栅极线的多个电压栅极线。 多个交叉点节点以跨越显示设备的伪随机顺序定位。

公开(公告)号：US20160334658A1

公开(公告)日：2016-11-17

申请号：US14712311

申请日：2015-05-14

Applicant: Apple Inc.

Inventor： Young-Jik Jo ,  Chun-Yao Huang ,  Hao-Lin Chiu ,  Kwang Soon Park ,  Shih Chang Chang

IPC: G02F1/133 ,  G02F1/1343

CPC classification number: G02F1/13306 ,  G02F1/134336 ,  G09G3/3655

Abstract: A display has an array of pixels controlled by display driver circuitry. Gate driver circuitry supplies gate line signals to rows of the pixels. The pixels may be liquid crystal display pixels. Each pixel may have a common electrode voltage terminal. The display may have a transparent conductive film that forms a common electrode voltage layer that overlaps that array and that is shorted to the common electrode voltage terminals of the pixels. Metal common electrode voltage lines may run across the transparent conductive film to reduce resistance. Metal common electrode voltage paths that are coupled to the metal common electrode voltage lines may run along the left and right edge of the display. Common electrode voltage compensation circuits may receive feedback from the metal common electrode voltage paths. There may be two or more common electrode voltage compensation circuits for both the left and right edges of the display.

Abstract translation: 显示器具有由显示驱动器电路控制的像素阵列。 栅极驱动器电路将栅极线信号提供给像素的行。 像素可以是液晶显示像素。 每个像素可以具有公共电极电压端子。 显示器可以具有形成与该阵列重叠并且与像素的公共电极电压端子短路的公共电极电压层的透明导电膜。 金属公共电极电压线可以穿过透明导电膜以降低电阻。 耦合到金属公共电极电压线的金属公共电极电压路径可以沿着显示器的左边缘和右边缘延伸。 公共电极电压补偿电路可以从金属公共电极电压路径接收反馈。 对于显示器的左边缘和右边缘都可以有两个或更多个公共电极电压补偿电路。

公开(公告)号：US11580905B2

公开(公告)日：2023-02-14

申请号：US17749045

申请日：2022-05-19

Applicant: Apple Inc.

Inventor： Rungrot Kitsomboonloha ,  Chin-Wei Lin ,  Shinya Ono ,  Gihoon Choo ,  Hao-Lin Chiu ,  Kyung Wook Kim ,  Pei-En Chang ,  Szu-Hsien Lee ,  Zino Lee

IPC: G09G3/3225

Abstract: A display may include an array of pixels that receive control signals from a chain of gate drivers. Each gate driver may include a logic sub-circuit and an output buffer sub-circuit. The output buffer sub-circuit may include depletion mode semiconducting oxide transistors with high mobility. The logic sub-circuit may include semiconducting oxide transistors, some of which can be depletion mode transistors and some of which can be enhancement mode transistors with lower mobility. The logic sub-circuit may include at least a carry circuit, a voltage setting circuit, an inverting circuit, a discharge circuit.

公开(公告)号：US10923012B1

公开(公告)日：2021-02-16

申请号：US16814879

申请日：2020-03-10

Applicant: Apple Inc.

Inventor： Jiaxi Hu ,  Hao-Lin Chiu ,  Shatam Agarwal ,  Kwang Soon Park ,  Joonggun Lee ,  Kyung Wook Kim ,  Shih Chang Chang ,  Fenghua Zheng

IPC: G09G3/20

Abstract: An electronic device may include a display. The display may include display driver circuitry that is configured to provide image data to columns of pixels and gate driver circuitry that is configured to provide control signals to rows of pixels. The display may be operable at a native refresh rate that is equal to the highest refresh rate at which the display has full resolution. The display may also be operable in a high refresh rate mode with a high refresh rate that is twice (or some other scaling factor greater than) the native refresh rate. To enable operation at the high refresh rate mode, vertical resolution of the display may be sacrificed. In other words, rows of pixels may be grouped together into effective rows that are then scanned in sequence. The gate driver circuitry may be formed as thin-film transistor circuitry or from gate driver integrated circuits.

公开(公告)号：US10157561B2

公开(公告)日：2018-12-18

申请号：US14863142

申请日：2015-09-23

Applicant: Apple Inc.

Inventor： Jin Yan ,  Young Cheol Yang ,  Jun Jiang ,  Hao-Lin Chiu ,  Young-Jik Jo ,  Cheng Chen

IPC: G09G3/20 ,  G09G3/36

Abstract: A display may have a first stage such as a color liquid crystal display stage and a second stage such as a monochromatic liquid crystal display stage that are coupled in tandem so that light from a backlight passes through both stages. The pixel pitch of the second stage may be greater than the pixel pitch of the first stage to ease alignment tolerances and reduce image processing complexity. The first stage may be provided with straight black masking strips, whereas the second stage may be provided with angled zigzagging black masking strips. The angle of the zigzagging black masking strips and the ratio of the pixel pitch of the second stage to that of the first stage may be selected to maximize optical transmittance while minimizing Moire effects.

公开(公告)号：US20170294172A1

公开(公告)日：2017-10-12

申请号：US15631410

申请日：2017-06-23

Applicant: Apple Inc.

Inventor： Byung Duk Yang ,  Szu-Hsien Lee ,  Kyung-Wook Kim ,  Shih Chang Chang ,  Chun-Yao Huang ,  Hao-Lin Chiu

IPC: G09G3/36 ,  G02F1/1362 ,  G06F3/041 ,  G02F1/1345 ,  G02F1/1368 ,  G06F3/044 ,  G02F1/1333 ,  G02F1/1343

CPC classification number: G09G3/3648 ,  G02F1/13338 ,  G02F1/134309 ,  G02F1/1345 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/13456 ,  G06F3/0412 ,  G06F3/0416 ,  G06F3/044 ,  G06F2203/04103 ,  G06F2203/04104 ,  G06F2203/04112 ,  G09F9/30 ,  G09G3/3666 ,  G09G3/3677 ,  G09G3/3688 ,  G09G2300/0413 ,  G09G2300/0426 ,  G09G2310/0281 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/124 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A display may have an array of pixels arranged in rows and columns. Each pixel may have a transistor for controlling the amount of output light associated with that pixel. The transistors may be thin-film transistors having active areas, first and second source-drain terminals, and gates. Gate lines may be used to distribute gate control signals to the gates of the transistors in each row. Data lines that run perpendicular to the gate lines may be used to distribute image data along columns of pixels. The gate lines may be connected to gate line extensions that run parallel to the data lines. The data lines may each overlap a respective one of the gate line extensions. Vias may be used to connect the gate line extensions to the gate lines. The gate line extensions may all have the same length.

公开(公告)号：US20160321975A1

公开(公告)日：2016-11-03

申请号：US14863142

申请日：2015-09-23

Applicant: Apple Inc.

Inventor： Jin Yan ,  Young Cheol Yang ,  Jun Jiang ,  Hao-Lin Chiu ,  Young-Jik Jo ,  Cheng Chen

IPC: G09G3/20 ,  G09G3/36

CPC classification number: G09G3/2003 ,  G09G3/3607 ,  G09G3/3648 ,  G09G2300/023 ,  G09G2320/0238 ,  G09G2320/0242

Abstract: A display may have a first stage such as a color liquid crystal display stage and a second stage such as a monochromatic liquid crystal display stage that are coupled in tandem so that light from a backlight passes through both stages. The pixel pitch of the second stage may be greater than the pixel pitch of the first stage to ease alignment tolerances and reduce image processing complexity. The first stage may be provided with straight black masking strips, whereas the second stage may be provided with angled zigzagging black masking strips. The angle of the zigzagging black masking strips and the ratio of the pixel pitch of the second stage to that of the first stage may be selected to maximize optical transmittance while minimizing Moire effects.

Abstract translation: 显示器可以具有第一级，例如彩色液晶显示级和第二级，例如单色液晶显示级，其串联耦合，使得来自背光的光通过两级。 第二级的像素间距可以大于第一级的像素间距，以减轻对准公差并降低图像处理的复杂性。 第一阶段可以设置有直黑色掩蔽条，而第二阶段可以设置有成角度的锯齿形黑色掩蔽条。 可以选择锯齿状黑色掩模条的角度和第二级的像素间距与第一级的像素间距的比率以使光线透射率最大化，同时最小化莫尔效应。