公开(公告)号：US11818681B2

公开(公告)日：2023-11-14

申请号：US17582785

申请日：2022-01-24

Applicant: Apple Inc.

Inventor： Jerrold V. Hauck ,  Alejandro J. Marquez ,  Timothy R. Paaske ,  Indranil S. Sen ,  Herve Sibert ,  Yannick L. Sierra ,  Raman S. Thiara

IPC: H04W64/00 ,  H04W12/03 ,  H04W12/033 ,  H04W12/041 ,  H04W12/062 ,  H04W12/63 ,  H04W12/065 ,  H04W12/069 ,  H04W12/0431 ,  H04W12/0433 ,  H04W12/0471 ,  H04W76/10 ,  H04L9/32 ,  H04L9/40 ,  H04W12/02 ,  H04W12/04 ,  H04W12/06 ,  H04W12/47 ,  H04W12/33 ,  H04W4/80

CPC classification number: H04W64/00 ,  H04L9/3273 ,  H04L63/061 ,  H04L63/0869 ,  H04W12/02 ,  H04W12/03 ,  H04W12/033 ,  H04W12/04 ,  H04W12/041 ,  H04W12/0431 ,  H04W12/0433 ,  H04W12/0471 ,  H04W12/06 ,  H04W12/062 ,  H04W12/065 ,  H04W12/069 ,  H04W12/63 ,  H04W76/10 ,  H04L63/0492 ,  H04W4/80 ,  H04W12/33 ,  H04W12/47

Abstract: A secure ranging system can use a secure processing system to deliver one or more ranging keys to a ranging radio on a device, and the ranging radio can derive locally at the system ranging codes based on the ranging keys. A deterministic random number generator can derive the ranging codes using the ranging key and one or more session parameters, and each device (e.g. a cellular telephone and another device) can independently derive the ranging codes and derive them contemporaneously with their use in ranging operations.

公开(公告)号：US09715262B2

公开(公告)日：2017-07-25

申请号：US14471759

申请日：2014-08-28

Applicant: Apple Inc.

Inventor： Wenbo Liu ,  Raman S. Thiara ,  Shingo Hatanaka

IPC: G06F1/26 ,  H04L7/08 ,  H04L25/03 ,  H04L25/02

CPC classification number: G06F1/266 ,  H04L25/0286 ,  H04L25/03

Abstract: A wired-line transmitter may include architecture that provides control of the current profile during power-up and/or power-down of the transmitter. The current profile may include a sloped ramp up during power-up and/or a sloped ramp down during power-down. The sloped ramps of the current profile mitigate supply bouncing during power-up and/or power-down. Individual enable signals may be derived from an enable signal provided to the transmitter. These individual enable signals may be provided (or turned off) in a time delayed (e.g., staggered) manner to provide the sloped ramps for the current profile.

公开(公告)号：US09306574B1

公开(公告)日：2016-04-05

申请号：US14638284

申请日：2015-03-04

Applicant: Apple Inc.

Inventor： Feng Zhao ,  Raman S. Thiara

IPC: H03K21/00 ,  H03K23/00 ,  H03K25/00 ,  H03K21/02 ,  H03K3/037 ,  H03L7/00

CPC classification number: H03K21/026 ,  H03K21/10 ,  H03L7/00

Abstract: The clock divider circuit includes a dividing circuit, a selection circuit, and a synchronization circuit. The dividing circuit is configured to receive an input clock signal at a first frequency, and to produce a number of different periodic signals based thereon. The selection circuit is configured to receive various ones of the periodic signals. An output clock signal may be provided from the selection circuit based on a selection made therein. The input clock signal may have a frequency that is an integer multiple of the output clock frequency. The selection circuit is configured to provide the output clock signal at different, selectable frequencies. The synchronization circuit may control the timing of the switching of the output clock signal from one frequency to the next so that such switching may be performed without glitches.

Abstract translation: 时钟分频电路包括分频电路，选择电路和同步电路。 分频电路被配置为以第一频率接收输入时钟信号，并且基于此产生多个不同的周期信号。 选择电路被配置为接收各种周期信号。 可以基于其中进行的选择从选择电路提供输出时钟信号。 输入时钟信号可以具有作为输出时钟频率的整数倍的频率。 选择电路被配置为以不同的可选频率提供输出时钟信号。 同步电路可以控制从一个频率到下一个频率的输出时钟信号的切换的定时，使得可以在没有毛刺的情况下执行这种切换。

公开(公告)号：US08963587B2

公开(公告)日：2015-02-24

申请号：US13893926

申请日：2013-05-14

Applicant: Apple Inc.

Inventor： Erik P. Machnicki ,  Raman S. Thiara ,  Shane J. Keil ,  Timothy J. Millet

IPC: H03K21/00

CPC classification number: H03K5/15013 ,  G06F1/04 ,  G06F1/08

Abstract: Embodiments of an apparatus are disclosed that may allow for changing the frequency of a clock coupled to a functional block within an integrated circuit. The apparatus may include a plurality of clock dividers and a multiplex circuit. Each of the plurality of clock dividers may divide the frequency of a base clock signal be a respective one of a plurality of divisors. The multiplex circuit may be configured to receive a plurality of selection signals, select an output from one of the plurality of clock dividers dependent upon the received selection signals, and coupled the selected output of the plurality of clock dividers to the functional block.

Abstract translation: 公开了可以允许改变耦合到集成电路内的功能块的时钟的频率的装置的实施例。 该装置可以包括多个时钟分频器和多路复用电路。 多个时钟分频器中的每一个可以将基本时钟信号的频率划分为多个除数中的相应一个。 多路复用电路可以被配置为接收多个选择信号，根据接收到的选择信号选择多个时钟分频器之一的输出，并将多个时钟分频器的选择输出耦合到功能块。

公开(公告)号：US20140340130A1

公开(公告)日：2014-11-20

申请号：US13893926

申请日：2013-05-14

Applicant: Apple Inc.

Inventor： Erik P. Machnicki ,  Raman S. Thiara ,  Shane J. Keil ,  Timothy J. Millet

IPC: H03K3/02

CPC classification number: H03K5/15013 ,  G06F1/04 ,  G06F1/08

Abstract: Embodiments of an apparatus are disclosed that may allow for changing the frequency of a clock coupled to a functional block within an integrated circuit. The apparatus may include a plurality of clock dividers and a multiplex circuit. Each of the plurality of clock dividers may divide the frequency of a base clock signal be a respective one of a plurality of divisors. The multiplex circuit may be configured to receive a plurality of selection signals, select an output from one of the plurality of clock dividers dependent upon the received selection signals, and coupled the selected output of the plurality of clock dividers to the functional block.

Abstract translation: 公开了可以允许改变耦合到集成电路内的功能块的时钟的频率的装置的实施例。 该装置可以包括多个时钟分频器和多路复用电路。 多个时钟分频器中的每一个可以将基本时钟信号的频率划分为多个除数中的相应一个。 多路复用电路可以被配置为接收多个选择信号，根据接收到的选择信号选择多个时钟分频器之一的输出，并将多个时钟分频器的选择输出耦合到功能块。