公开(公告)号：US08862935B2

公开(公告)日：2014-10-14

申请号：US14143352

申请日：2013-12-30

Applicant: ARM Limited

Inventor： Shidhartha Das ,  David Michael Bull ,  Emre Ozer

IPC: G06F11/00 ,  G06F11/07 ,  G06F11/16 ,  G06F11/10 ,  G01R31/3181

CPC classification number: G06F11/0793 ,  G01R31/31816 ,  G06F11/1076 ,  G06F11/1608

Abstract: An integrated circuit is provided with error detection circuitry and error repair circuitry. Error tolerance circuitry is responsive to a control parameter to selectively disable the error repair circuitry. The control parameter is dependent on the processing performed within the circuit. For example, the control parameter may be generated in dependence upon the program instruction being executed, the output signal value which is in error, the previous behavior of the circuit or in other ways.

Abstract translation: 集成电路具有错误检测电路和错误修复电路。 误差容限电路响应于控制参数来选择性地禁用错误修复电路。 控制参数取决于电路内执行的处理。 例如，控制参数可以根据执行的程序指令，错误的输出信号值，电路的先前行为或其他方式来生成。

公开(公告)号：US20200226095A1

公开(公告)日：2020-07-16

申请号：US16645993

申请日：2018-09-25

Applicant: Arm Limited

Inventor： Mbou Eyole ,  Emre Ozer ,  Xabier Iturbe ,  Shidhartha Das

IPC: G06F15/78 ,  G11C14/00 ,  H03K19/17728

Abstract: A method of reconfiguration and a reconfigurable circuit architecture comprising a configurable volatile storage circuit and Non-Volatile Memory circuit elements; wherein the Non-Volatile memory circuit elements store multiple bit states for re-configuration, the multiple bit states being read from the Non-Volatile memory circuit elements and written into the configurable volatile storage circuit for reconfiguration. The Non-Volatile Memory circuit elements and the configurable volatile storage circuit are provided on a common die.

公开(公告)号：US10657010B2

公开(公告)日：2020-05-19

申请号：US15800145

申请日：2017-11-01

Applicant: ARM Limited

Inventor： Xabier Iturbe ,  Emre Ozer ,  Balaji Venu

IPC: G06F11/00 ,  G06F11/16 ,  G06F11/10 ,  G06F11/18 ,  G06F11/07

Abstract: An apparatus 2 comprises at least three processing circuits 4 to perform redundant processing of a common thread of program instructions. Error detection circuitry 16 is provided comprising a number of comparators 22 for detecting a mismatch between signals on corresponding signal nodes 20 in the processing circuits 4. When a comparator 22 detects a mismatch, this triggers a recovery process. The error detection circuitry 16 generates an unresolvable error signal 36 indicating that a detected area is unresolvable by the recovery process when, during the recovery process, a mismatch is detected by one of the proper subset 34 of the comparators 22. By considering fewer comparators 22 during the recovery process than during normal operation, the chances of unrecoverable errors being detected can be reduced, increasing system availability.

公开(公告)号：US20200070848A1

公开(公告)日：2020-03-05

申请号：US16118277

申请日：2018-08-30

Applicant: Arm Limited

Inventor： Emre Ozer

IPC: B60W50/08 ,  B60W40/08 ,  B60W40/02 ,  B60W30/10

Abstract: The present techniques generally relate to a computer implemented method of initiating autonomous drive of a vehicle when the drive of the vehicle is under the control of a user, the method comprising: detecting or predicting the start of a user sneezing episode; and initiating autonomous drive of the vehicle during the user sneezing episode. The method may additionally involve, after the initiating the autonomous drive of the vehicle, determining the end of the user sneezing episode, ending the autonomous drive of the vehicle and reverting the drive of the vehicle back to the control of the user. All of this may be done without the user of the vehicle being aware of the autonomous drive of the vehicle.

公开(公告)号：US09116844B2

公开(公告)日：2015-08-25

申请号：US14246162

申请日：2014-04-07

Applicant: ARM Limited

Inventor： Emre Ozer ,  Yiannakis Sazeides ,  Daniel Kershaw ,  Stuart David Biles

IPC: G06F11/00 ,  G06F11/14 ,  G06F11/07

CPC classification number: G06F11/1415 ,  G06F11/0727 ,  G06F11/076 ,  G06F11/0787 ,  G06F2201/86

Abstract: A data processing apparatus has a plurality of storage elements residing at different physical locations within the apparatus, and fault history circuitry for detecting local transient faults occurring in each storage element, and for maintaining global transient fault history data based on the detected local transient faults. Analysis circuitry monitors the global transient fault history data to determine, based on predetermined criteria, whether the global transient fault history data is indicative of random transient faults occurring within the data processing apparatus, or is indicative of a coordinated transient fault attack. The analysis circuitry is then configured to initiate a countermeasure action on determination of a coordinated transient fault attack. This provides a simple and effective mechanism for distinguishing between random transient faults that may naturally occur, and a coordinated transient fault attack that may be initiated in an attempt to circumvent the security of the data processing apparatus.

Abstract translation: 数据处理装置具有驻留在装置内的不同物理位置的多个存储元件，以及故障历史电路，用于检测每个存储元件中发生的局部瞬态故障，并且用于基于检测到的局部瞬态故障来维护全局瞬态故障历史数据。 分析电路监视全局瞬态故障历史数据，以基于预定标准确定全局瞬态故障历史数据是否表示在数据处理装置内发生的随机瞬态故障，或指示协调的瞬时故障攻击。 分析电路然后被配置为启动对协调的瞬态故障攻击的确定的对策动作。 这提供了一种用于区分可能自然发生的随机瞬态故障的简单和有效的机制，以及可以在试图绕过数据处理设备的安全性时发起的协调的瞬态故障攻击。

公开(公告)号：US11176012B2

公开(公告)日：2021-11-16

申请号：US16823180

申请日：2020-03-18

Applicant: Arm Limited

Inventor： Emre Ozer ,  Xabier Iturbe ,  Balaji Venu

IPC: G06F11/00 ,  G06F11/27 ,  G06F11/22 ,  G06F11/16

Abstract: Briefly, example methods, apparatuses, and/or articles of manufacture are disclosed that may be implemented, in whole or in part, to determine indicators of potential errors in a multi-processing core lockstep computing device comprising a plurality of processing cores, based, at least in part, on observations of output signals generated by at least two processing cores of the plurality of processing cores. A built-in self-test (BIST) procedure may then be based, at least in part, on the determining indicators.

公开(公告)号：US09021298B2

公开(公告)日：2015-04-28

申请号：US14143065

申请日：2013-12-30

Applicant: ARM Limited

Inventor： Shidhartha Das ,  David Michael Bull ,  Emre Ozer

IPC: G06F11/00 ,  G06F11/07 ,  G01R31/3181 ,  G06F11/10 ,  G06F11/16

CPC classification number: G06F11/0793 ,  G01R31/31816 ,  G06F11/1076 ,  G06F11/1608

Abstract: An integrated circuit is provided with error detection circuitry and error repair circuitry. Error tolerance circuitry is responsive to a control parameter to selectively disable the error repair circuitry. The control parameter is dependent on the processing performed within the circuit. For example, the control parameter may be generated in dependence upon the program instruction being executed, the output signal value which is in error, the previous behavior of the circuit or in other ways.

Abstract translation: 集成电路具有错误检测电路和错误修复电路。 误差容限电路响应于控制参数来选择性地禁用错误修复电路。 控制参数取决于电路内执行的处理。 例如，控制参数可以根据执行的程序指令，错误的输出信号值，电路的先前行为或其他方式来生成。

公开(公告)号：US20140115377A1

公开(公告)日：2014-04-24

申请号：US14143352

申请日：2013-12-30

Applicant: ARM Limited

Inventor： Shidhartha DAS ,  David Michael Bull ,  Emre Ozer

IPC: G06F11/07

CPC classification number: G06F11/0793 ,  G01R31/31816 ,  G06F11/1076 ,  G06F11/1608

Abstract: An integrated circuit is provided with error detection circuitry and error repair circuitry. Error tolerance circuitry is responsive to a control parameter to selectively disable the error repair circuitry. The control parameter is dependent on the processing performed within the circuit. For example, the control parameter may be generated in dependence upon the program instruction being executed, the output signal value which is in error, the previous behavior of the circuit or in other ways.