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    Selecting instructions for a value predictor
    1.
    发明授权
    Selecting instructions for a value predictor 有权

    公开(公告)号：US11409532B1

    公开(公告)日：2022-08-09

    申请号：US17215429

    申请日：2021-03-29

    Applicant: Arm Limited

    Inventor： Vladimir Vasekin ,  David Michael Bull ,  Sanghyun Park ,  Alexei Fedorov

    IPC: G06F9/30 ,  G06F9/38 ,  G06F9/50 ,  G06F9/32

    Abstract: Apparatuses and methods of data processing are disclosed for processing circuitry having a pipeline of multiple stages. Value prediction storage circuitry holds value predictions, each associated with an instruction identifier. The value prediction storage circuitry performs look-ups and provides the processing circuitry with data value predictions. The processing circuitry speculatively issues a subsequent instruction into the pipeline by provisionally assuming that execution of a primary instruction will result in the generated data value prediction. Allocation of entries into the value prediction storage circuitry is based on a dynamic allocation policy, whereby likelihood of allocation into the value prediction storage circuitry of an data value prediction increases for an executed instruction when the executed instruction is associated with at least one empty processing stage in the pipeline.

    Apparatus and method for using predicted result values
    2.
    发明授权
    Apparatus and method for using predicted result values 有权

    公开(公告)号：US10719329B2

    公开(公告)日：2020-07-21

    申请号：US16021178

    申请日：2018-06-28

    Applicant: Arm Limited

    Inventor： Vladimir Vasekin ,  David Michael Bull ,  Chiloda Ashan Senarath Pathirane ,  Alexei Fedorov

    IPC: G06F9/38 ,  G06F21/64 ,  G06F9/30 ,  G06F9/54

    Abstract: An apparatus and method are provided for using predicted result values. The apparatus has a processing unit that comprises processing circuitry for executing a sequence of instructions, and value prediction circuitry for identifying a predicted result value for at least one instruction. A result producing structure is provided that is responsive to a request issued from the processing unit when the processing circuitry is executing a first instruction, to produce a result value for the first instruction and return that result value to the processing unit. While waiting for the result value from the result producing structure, the processing circuitry can be arranged to speculatively execute at least one dependent instruction using a predicted result value for the first instruction as obtained from the value prediction circuitry. The request issued from the processing unit includes a signature value indicative of the predicted result value, and the result producing structure references the signature value in order to detect whether a mispredict condition exists indicating that the predicted result value differs from the result value. The apparatus further provides a mispredict signal transmission path via which the result producing structure, when the mispredict condition is detected, can assert a mispredict signal for receipt by the processing unit prior to the result value being available to the processing unit. Such an approach can reduce the misprediction penalty associated with using a mispredicted result value.

    Smart surface covering and structure having remotely interrogatable antenna node array for remote integrity checking
    3.
    发明授权
    Smart surface covering and structure having remotely interrogatable antenna node array for remote integrity checking 有权

    公开(公告)号：US10303906B1

    公开(公告)日：2019-05-28

    申请号：US15825467

    申请日：2017-11-29

    Applicant: Arm Limited

    Inventor： James Edward Myers ,  David Michael Bull ,  Edgar H. Callaway, Jr.

    IPC: H04Q5/22 ,  G06K7/10 ,  G06K7/00 ,  G01V1/00 ,  G01M5/00

    Abstract: A method, system and surface covering for enabling wireless detection of damage to a structure is disclosed. At least one array having a plurality of nodes are coupled to a surface covering, such as at least one of a wall, ceiling and floor covering for a least a portion of the structure. An electronic reader is operable to wirelessly interrogate the array and read return signals from nodes in the array. The return signals contain data representing an ID for corresponding responsive nodes in the array, and the returned IDs are extracted and compared to a plurality of IDs stored in a data store for nodes in any given array. A mismatch between the returned and stored IDs for the nodes in the array indicates a structural defect in a respective portion of the structure overlaid by the floor/wall covering.

    Integrated circuit with error repair and fault tolerance
    5.
    发明授权
    Integrated circuit with error repair and fault tolerance 有权
    具有错误修复和容错功能的集成电路

    公开(公告)号：US09021298B2

    公开(公告)日：2015-04-28

    申请号：US14143065

    申请日：2013-12-30

    Applicant: ARM Limited

    Inventor： Shidhartha Das ,  David Michael Bull ,  Emre Ozer

    IPC: G06F11/00 ,  G06F11/07 ,  G01R31/3181 ,  G06F11/10 ,  G06F11/16

    CPC classification number: G06F11/0793 ,  G01R31/31816 ,  G06F11/1076 ,  G06F11/1608

    Abstract: An integrated circuit is provided with error detection circuitry and error repair circuitry. Error tolerance circuitry is responsive to a control parameter to selectively disable the error repair circuitry. The control parameter is dependent on the processing performed within the circuit. For example, the control parameter may be generated in dependence upon the program instruction being executed, the output signal value which is in error, the previous behavior of the circuit or in other ways.

    Abstract translation: 集成电路具有错误检测电路和错误修复电路。 误差容限电路响应于控制参数来选择性地禁用错误修复电路。 控制参数取决于电路内执行的处理。 例如，控制参数可以根据执行的程序指令，错误的输出信号值，电路的先前行为或其他方式来生成。

    Method and apparatus for comparing predicated load value with masked load value
    7.
    发明授权
    Method and apparatus for comparing predicated load value with masked load value 有权

    公开(公告)号：US11366668B1

    公开(公告)日：2022-06-21

    申请号：US17114970

    申请日：2020-12-08

    Applicant: Arm Limited

    Inventor： Vladimir Vasekin ,  David Michael Bull ,  Sanghyun Park ,  Alexei Fedorov

    IPC: G06F9/38 ,  G06F9/30

    Abstract: A digital processor, method, and a non-transitory computer readable storage medium are described, and include a load pipeline operative to access a data content and convert the data content into a load result. The digital processor also includes a value prediction check circuit that is operative to access a speculative content, determine a predicted value from the speculative content, and determine a masked value by masking the data content with a data mask. The masked value is compared to the predicted value, and an action associated with the load result is commanded based upon the comparing of the masked value and the predicted value.

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