公开(公告)号：US11983533B2

公开(公告)日：2024-05-14

申请号：US17851266

申请日：2022-06-28

Applicant: Arm Limited

Inventor： Joseph Michael Pusdesris ,  Alexander Cole Shulyak ,  Yasuo Ishii ,  Houdhaifa Bouzguarrou

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30058 ,  G06F9/3861

Abstract: There is provided a data processing apparatus comprising history storage circuitry that stores sets of behaviours of helper instructions for a control flow instruction. Pointer storage circuitry stores pointers, each associated with one of the sets. The behaviours in the one of the sets are indexed according to one of the pointers associated with that one of the sets. Increment circuitry increments at least some of the pointers in response to an increment event and prediction circuitry determines a predicted behaviour of the control flow instruction using one of the sets of behaviours.

公开(公告)号：US11907723B2

公开(公告)日：2024-02-20

申请号：US17699326

申请日：2022-03-21

Applicant: Arm Limited

Inventor： Nicholas Andrew Plante ,  Joseph Michael Pusdesris ,  Jungsoo Kim

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/384 ,  G06F9/30029 ,  G06F9/30079 ,  G06F9/30181

Abstract: A data processing apparatus is provided. Rename circuitry performs a register rename stage of a pipeline by storing, in storage circuitry, mappings between registers. Each of the mappings is associated with an elimination field value. Operation elimination circuitry replaces an operation that indicates an action is to be performed on data from a source register and stored in a destination register, with a new mapping in the storage circuitry that references the destination register and has the elimination field value set. Operation circuitry responds to a subsequent operation that accesses the destination register when the elimination field value is set; by obtaining contents of the source register, performing the action on the contents to obtain a result, and returning the result.

公开(公告)号：US11334495B2

公开(公告)日：2022-05-17

申请号：US16549291

申请日：2019-08-23

Applicant: Arm Limited

Inventor： Joseph Michael Pusdesris ,  Yasuo Ishii

IPC: G06F12/0891 ,  G06F12/0875 ,  G06F9/30

Abstract: A data processing apparatus is provided. It includes cache circuitry to store a plurality of items, each having an associated indicator. Processing circuitry executes instructions using at least some of the plurality of items. Fill circuitry inserts a new item into the cache circuitry. Eviction circuitry determines which of the plurality of items is to be a victim item based on the indicator, and evicts the victim item from the cache circuitry. Detection circuitry detects a state of the processing circuitry at a time that the new item is inserted into the cache circuitry, and sets the indicator in dependence on the state.

公开(公告)号：US10769070B2

公开(公告)日：2020-09-08

申请号：US16140625

申请日：2018-09-25

Applicant: Arm Limited

Inventor： Joseph Michael Pusdesris ,  Miles Robert Dooley ,  Alexander Cole Shulyak ,  Krishnendra Nathella ,  Dam Sunwoo

IPC: G06F12/0862 ,  G06F9/30 ,  G06F5/06

Abstract: Apparatuses and methods for prefetch generation are disclosed. Prefetching circuitry receives addresses specified by load instructions and can cause retrieval of a data value from an address before that address is received. Stride determination circuitry determines stride values as a difference between a current address and a previously received address. Plural stride values corresponding to a sequence of received addresses are determined. Multiple stride storage circuitry stores the plurality of stride values determined by the stride determination circuitry. New address comparison circuitry determines whether a current address corresponds to a matching stride value based on the plurality of stride values stored in the multiple stride storage circuitry. Prefetch initiation circuitry can causes a data value to be retrieved from a further address, wherein the further address is the current address modified by the matching stride value of the plurality of stride values. By the use of multiple stride values, more complex load address patterns can be prefetched.

公开(公告)号：US10402349B2

公开(公告)日：2019-09-03

申请号：US15427391

申请日：2017-02-08

Applicant: ARM Limited

Inventor： Michael Filippo ,  Jamshed Jalal ,  Klas Magnus Bruce ,  Paul Gilbert Meyer ,  David Joseph Hawkins ,  Phanindra Kumar Mannava ,  Joseph Michael Pusdesris

IPC: G06F13/16 ,  G06F13/364 ,  G06F12/0864 ,  G06F13/42 ,  G06F13/40 ,  G06F12/0831 ,  G06F12/0844

Abstract: A memory controller comprises memory access circuitry configured to initiate a data access of data stored in a memory in response to a data access hint message received from another node in data communication with the memory controller; to access data stored in the memory in response to a data access request received from another node in data communication with the memory controller and to provide the accessed data as a data access response to the data access request.

公开(公告)号：US11693666B2

公开(公告)日：2023-07-04

申请号：US17505854

申请日：2021-10-20

Applicant: Arm Limited

Inventor： Joseph Michael Pusdesris ,  Nicholas Andrew Plante ,  Yasuo Ishii ,  Chris Abernathy

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/345

CPC classification number: G06F9/3861 ,  G06F9/30018 ,  G06F9/30072 ,  G06F9/30101 ,  G06F9/3455 ,  G06F9/3844 ,  G06F9/3848 ,  G06F9/3859

Abstract: A predicated-loop-terminating branch instruction controls, based on whether a loop termination condition is satisfied, whether the processing circuitry should process a further iteration of a predicated loop body or process a following instruction. If at least one unnecessary iteration of the predicated loop body is processed following a mispredicted-non-termination branch misprediction when the loop termination condition is mispredicted as unsatisfied for a given iteration when it should have been satisfied, processing of the at least one unnecessary iteration of the predicated loop body is predicated to suppress an effect of the at least one unnecessary iteration. When the mispredicted-non-termination branch misprediction is detected for the given iteration of the predicated-loop-terminating branch instruction, in response to determining that a flush suppressing condition is satisfied, flushing of the at least one unnecessary iteration of the predicated loop body is suppressed as a response to the mispredicted-non-termination branch misprediction.

公开(公告)号：US11385896B2

公开(公告)日：2022-07-12

申请号：US15930907

申请日：2020-05-13

Applicant: Arm Limited

Inventor： Alexander Cole Shulyak ,  Joseph Michael Pusdesris ,  Adrian Montero ,  Balaji Vijayan

IPC: G06F9/38 ,  G06F9/345

Abstract: An apparatus and method are provided. The apparatus comprises storage circuitry to store a plurality of data elements. Processing circuitry executes a stream of instructions comprising access instructions that access some of the data elements at given locations. Training circuitry determines a pattern of the given locations based on the access instructions. Prefetch circuitry performs prefetches based on the pattern and filter circuitry filters the access instructions used by the training circuitry to determine the pattern by including discontinuous access instructions whose given location raises a discontinuity with the given location of a previous access instruction. In this way, it is possible to perform prefetching by calculating, rather than guessing, at a cumulative stride between the access instructions.

公开(公告)号：US11204878B1

公开(公告)日：2021-12-21

申请号：US17065834

申请日：2020-10-08

Applicant: Arm Limited

Inventor： Joseph Michael Pusdesris ,  Chris Abernathy

IPC: G06F12/0897 ,  G06F12/0862 ,  G06F9/30 ,  G06F12/02 ,  G06F12/0811

Abstract: An apparatus is provided that includes a memory hierarchy comprising a plurality of caches and a memory. Prefetch circuitry acquires data from the memory hierarchy before the data is explicitly requested by processing circuitry configured to execute a stream of instructions. Writeback circuitry causes the data to be written back from a higher level cache of the memory hierarchy to a lower level cache of the memory hierarchy and tracking circuitry tracks a proportion of entries that are stored in the lower level cache of the memory hierarchy having been written back from the higher level cache of the memory hierarchy, that are subsequently explicitly requested by the processing circuitry in response to one of the instructions.

公开(公告)号：US11188475B1

公开(公告)日：2021-11-30

申请号：US17061965

申请日：2020-10-02

Applicant: Arm Limited

Inventor： Joseph Michael Pusdesris ,  Balaji Vijayan

IPC: G06F12/0897 ,  G06F12/0871 ,  G06F12/14 ,  G06F12/02 ,  G06F12/0864

Abstract: A technique is provided for managing caches in a cache hierarchy. An apparatus has processing circuitry for performing operations and a plurality of caches for storing data for reference by the processing circuitry when performing the operations. The plurality of caches form a cache hierarchy including a given cache at a given hierarchical level and a further cache at a higher hierarchical level. The given cache is a set associative cache having a plurality of cache ways, and the given cache and the further cache are arranged such that the further cache stores a subset of the data in the given cache. In response to an allocation event causing data for a given memory address to be stored in the further cache, the given cache issues a way indication to the further cache identifying which cache way in the given cache the data for the given memory address is stored in. In response to the allocation event, the further cache not only stores the data for the given memory address, but also retains the way indication whilst the data for the given memory address remains stored within the further cache. When the further cache subsequently issues a message to the given cache relating to the data for the given memory address, it provides the way indication to the given cache for use in controlling an access to the given cache.

公开(公告)号：US10990403B1

公开(公告)日：2021-04-27

申请号：US16752995

申请日：2020-01-27

Applicant: Arm Limited

Inventor： Joseph Michael Pusdesris ,  Yasuo Ishii ,  Muhammad Umar Farooq

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/48

Abstract: An apparatus is described, comprising processing circuitry to speculatively execute an earlier instruction and a later instruction by generating a prediction of an outcome of the earlier instruction and a prediction of an outcome of the later instruction, wherein the prediction of the outcome of the earlier instruction causes a first control flow path to be executed. The apparatus also comprises storage circuitry to store the outcome of the later instruction in response to the later instruction completing, and flush circuitry to generate a flush in response to the prediction of the outcome of the earlier instruction being incorrect. When re-executing the later instruction in a second control flow path following the flush, the processing circuitry is adapted to generate the prediction of the outcome of the later instruction as the outcome stored in the storage circuitry during execution of the first control flow path.