公开(公告)号：US10204894B2

公开(公告)日：2019-02-12

申请号：US15259256

申请日：2016-09-08

Applicant: ARM Limited

Inventor： Marlin Wayne Frederick, Jr.

IPC: H01L23/52 ,  H01L21/4763 ,  G06F17/50 ,  H01L27/02 ,  H01L23/528 ,  H01L21/768 ,  H01L23/522

Abstract: An integrated circuit layout includes a routing layout of routing conductors and routing connection vias formed prior to a power grid connection which forms power connection vias between power grid conductors and standard-power cell conductors within the standard cells. This enables a minimum via spacing requirement to be met while permitting an increased flexibility in the positioning of the routing connection vias.

公开(公告)号：US11836432B2

公开(公告)日：2023-12-05

申请号：US17091229

申请日：2020-11-06

Applicant: Arm Limited

Inventor： Sharath Koodali Edathil ,  Marlin Wayne Frederick, Jr.

IPC: G06F30/398 ,  G06F30/373 ,  G06F30/327 ,  G06F30/394

CPC classification number: G06F30/373 ,  G06F30/327 ,  G06F30/394 ,  G06F30/398

Abstract: Various implementations described herein refer to a method. The method may be configured to synthesize standard cells for a physical design having a power supply net with power supply rails. The method may be configured to employ a place-and-route tool so as to define edge-types for each standard cell of the standard cells in the physical design based on the power supply net and the power supply rails that touch at least one edge of each standard cell of the standard cells.

公开(公告)号：US11068639B2

公开(公告)日：2021-07-20

申请号：US16165675

申请日：2018-10-19

Applicant: Arm Limited

Inventor： Marlin Wayne Frederick, Jr. ,  Ettore Amirante ,  Ronald Paxton Preston ,  Andy Wangkun Chen ,  Sriram Thyagarajan ,  Yew Keong Chong

IPC: G06F30/39 ,  G06F30/394 ,  G11C11/419 ,  G11C7/12

Abstract: Various implementations described herein refer to a method. The method may include providing a metal layout for an integrated circuit, wherein the metal layout includes multiple lines associated with bitlines. The method may include inserting at least one additional line between the multiple lines and the bitlines. The method may include arranging the at least one additional line with respect to the multiple lines and the bitlines so as to reduce capacitance associated with the bitlines.

公开(公告)号：US09871039B2

公开(公告)日：2018-01-16

申请号：US14981449

申请日：2015-12-28

Applicant: ARM Limited

Inventor： Jean-Luc Pelloie ,  Marlin Wayne Frederick, Jr.

IPC: H01L21/70 ,  H01L27/088 ,  H01L25/00 ,  G06F17/50 ,  H01L27/092 ,  H01L21/8238 ,  H01L23/522 ,  H01L23/528 ,  H01L27/02

CPC classification number: H01L27/092 ,  H01L21/823871 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0207

Abstract: Various implementations described herein are directed to an integrated circuit with mitigated resistance. The integrated circuit may include a cell having a plurality of transistors including a first transistor of a first type and a second transistor of a second type that is different from the first type. The integrated circuit may include a first wire coupling the first transistor to the second transistor. The integrated circuit may include a second wire coupling the first wire to an output routing wire. The integrated circuit may include a redundant wire further coupling the first wire to the output routing wire.

公开(公告)号：US09690889B2

公开(公告)日：2017-06-27

申请号：US15239991

申请日：2016-08-18

Applicant: ARM LIMITED

Inventor： Marlin Wayne Frederick, Jr. ,  Karen Lee Delk ,  Lena Ahlen ,  James Dennis Dodrill

IPC: G06F9/455 ,  G06F17/50

CPC classification number: G06F17/5031 ,  G06F17/5081 ,  G06F2217/84

Abstract: A static timing analysis method that determines an expected design condition surrounding a target cell in an integrated circuit design. A derate adjustment is determined based on the expected design condition for a target cell and a timing derate, representing variation in propagation delay for a default design condition, is then adjusted based on the derate adjustment. An expected timing of a signal path including the target cell is determined based on the adjusted timing derate. The derate adjustment may be determined based on simulated variance of the propagation delay through the target cell for the expected design condition. This approach avoids unnecessary optimism or pessimism in the timing derate, which reduces the number of false positive or false negative detections of timing violations in the static timing analysis.

公开(公告)号：US09454633B2

公开(公告)日：2016-09-27

申请号：US14307565

申请日：2014-06-18

Applicant: ARM LIMITED

Inventor： Marlin Wayne Frederick, Jr.

IPC: G06F17/50 ,  H01L23/528 ,  H01L27/02

CPC classification number: H01L27/0207 ,  G06F17/5068 ,  G06F17/5077 ,  G06F17/5081 ,  G06F2217/06 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/5286 ,  H01L27/0203 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit layout is formed by performing a routing step forming a routing layout of routing conductors and routing connection vias prior to performing a power grid connection step which forms power connection vias between power grid conductors and standard-power cell conductors within the standard cells. This enables a minimum via spacing requirement to be met while permitting an increased flexibility in the positioning of the routing connection vias.

Abstract translation: 通过在执行电网连接步骤之前执行形成路由导体的布线布局和路由连接通孔的路由步骤来形成集成电路布局，所述电网连接步骤在电力网格导体与标准单元内的标准功率单元导体之间形成电力连接通路。 这使得能够满足最小通孔间隔要求，同时允许在路线连接通孔的定位中增加灵活性。

公开(公告)号：US08959472B1

公开(公告)日：2015-02-17

申请号：US14039224

申请日：2013-09-27

Applicant: ARM Limited

Inventor： Marlin Wayne Frederick, Jr. ,  Jean-Luc Pelloie

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5077

Abstract: A method of generating an integrated circuit layout comprises a step of determining a placement of standard cells selected from a standard cell library while permitting boundary conflicts in which incompatible boundary regions of standard cells are placed next to each other. After determining routing connections between the standard cells, the integrated circuit layout is generated. The generation of the integrated circuit layout includes a mapping step of mapping at least one incompatible boundary region to an alternative boundary region to resolve at least one boundary conflict.

Abstract translation: 一种生成集成电路布局的方法包括以下步骤：确定从标准单元库选择的标准单元的放置，同时允许标准单元的不兼容边界区域彼此相邻放置的边界冲突。 在确定标准单元之间的路由连接之后，生成集成电路布局。 集成电路布局的生成包括将至少一个不兼容的边界区域映射到替代边界区域以解决至少一个边界冲突的映射步骤。

公开(公告)号：US11011222B2

公开(公告)日：2021-05-18

申请号：US16294577

申请日：2019-03-06

Applicant: Arm Limited

Inventor： Marlin Wayne Frederick, Jr. ,  Ronald Paxton Preston ,  Andy Wangkun Chen ,  Yew Keong Chong

IPC: G11C11/412 ,  G11C11/419

Abstract: Various implementations described herein refer to an integrated circuit having an array of bitcells coupled between at least one pair of bitlines including a first bitline and a second bitline that is a complement of the first bitline. The integrated circuit may include at least one pair of ancillary lines disposed adjacent to the at least one pair of bitlines, and the at least one pair of ancillary lines include a first ancillary line disposed adjacent to the first bitline and a second ancillary line disposed adjacent to the second bitline. The integrated circuit may include multiple pairs of passgates coupled between the at least one pair of bitlines and the at least one pair of ancillary lines.

公开(公告)号：US10210303B2

公开(公告)日：2019-02-19

申请号：US15418613

申请日：2017-01-27

Applicant: ARM Limited

Inventor： Ravindra Narayana Rao ,  Marlin Wayne Frederick, Jr. ,  Karen Lee Delk ,  Stefan Charles Creaser

IPC: G06F17/50

Abstract: Various implementations described herein are directed to an apparatus having a receiver module that receives a floorplan of an integrated circuit having power gates, an obstruction, and a control pin for providing a sleep signal. The apparatus can include an identifier module that identifies where the obstruction interrupts a sequence of the power gates, organizes the sequence of the power gates into a column, and divides the column into segments in which a first segment lies below the obstruction, a second segment lies above the obstruction, and a third segment is offset from the first segment and the second segment. The apparatus can include a stitcher module that performs a sleep signal stitching for the integrated circuit by distributing the sleep signal from the control pin to the power gates that include each power gate in each of the first segment, the second segment, and the third segment.

公开(公告)号：US10083833B1

公开(公告)日：2018-09-25

申请号：US15629684

申请日：2017-06-21

Applicant: ARM Limited

Inventor： Ronald Paxton Preston ,  Marlin Wayne Frederick, Jr.

IPC: H01L21/033

CPC classification number: H01L21/0338 ,  G03F1/36 ,  G03F7/70441 ,  G06F17/5036 ,  G06F17/5068

Abstract: Various implementations described herein are directed to a method for manufacturing an integrated circuit. The method may include defining multiple lithographic regions for the integrated circuit, and the multiple lithographic regions may include a first lithographic region and a second lithographic region. The method may include defining an anchor in the first lithographic region and defining a target in the second lithographic region. The method may include defining a spacing interval between the anchor and the target. The method may include inserting an integration fill in the spacing interval.