公开(公告)号：US11676656B2

公开(公告)日：2023-06-13

申请号：US17168428

申请日：2021-02-05

Applicant: Arm Limited

Inventor： Andy Wangkun Chen ,  Yew Keong Chong ,  Rajiv Kumar Sisodia ,  Sriram Thyagarajan

IPC: G11C11/419 ,  G11C11/412

CPC classification number: G11C11/419 ,  G11C11/412

Abstract: Various implementations described herein are related to a device having memory circuitry with bitlines coupled to an array of bitcells. Also, the device may have first precharge circuitry that precharges the bitlines before a write cycle. Also, the device may have second precharge circuitry that precharges the bitlines after the write cycle.

公开(公告)号：US20220254411A1

公开(公告)日：2022-08-11

申请号：US17168428

申请日：2021-02-05

Applicant: Arm Limited

Inventor： Andy Wangkun Chen ,  Yew Keong Chong ,  Rajiv Kumar Sisodia ,  Sriram Thyagarajan

IPC: G11C11/419 ,  G11C11/412

Abstract: Various implementations described herein are related to a device having memory circuitry with bitlines coupled to an array of bitcells. Also, the device may have first precharge circuitry that precharges the bitlines before a write cycle. Also, the device may have second precharge circuitry that precharges the bitlines after the write cycle.

公开(公告)号：US11380384B2

公开(公告)日：2022-07-05

申请号：US17006689

申请日：2020-08-28

Applicant: Arm Limited

Inventor： Andy Wangkun Chen ,  Sriram Thyagarajan ,  Yew Keong Chong ,  Sony ,  Ettore Amirante ,  Ayush Kulshrestha

IPC: G11C5/14 ,  G11C11/4074 ,  G11C11/4094 ,  G11C7/10 ,  G11C11/4091 ,  G11C11/413

Abstract: Various implementations described herein are related to a device having memory circuitry with a bitcell array. The device may include a frontside power network that is coupled to the bitcell array, and the device may include a backside power network that provides power to the bitcell array. The device may include transition vias that couple the backside power network to the frontside power network, and the backside power network may provide power to the bitcell array by way of the transition vias being coupled to the frontside power network.

公开(公告)号：US11200922B2

公开(公告)日：2021-12-14

申请号：US16725779

申请日：2019-12-23

Applicant: Arm Limited

Inventor： Sriram Thyagarajan ,  Andy Wangkun Chen ,  Yew Keong Chong ,  Munish Kumar

IPC: G11C7/10 ,  G11C7/22

Abstract: Various implementations described herein are related to a device having memory circuitry and multiplexer circuitry. The memory circuitry may include a single bank of memory cells that are arranged in multiple columns, and each column of the multiple columns may provide singe-bit data. The multiplexer circuitry may include multiplexer logic that receives the single-bit data from each column of the multiple columns and provides selected data as output data.

公开(公告)号：US20210241807A1

公开(公告)日：2021-08-05

申请号：US16783104

申请日：2020-02-05

Applicant: Arm Limited

Inventor： Andy Wangkun Chen ,  Yew Keong Chong ,  Sriram Thyagarajan

IPC: G11C8/10 ,  G11C7/06 ,  G11C7/10 ,  G11C7/12 ,  G11C7/22

Abstract: According to one implementation of the present disclosure, an integrated circuit includes first and second word-line decoder circuitry; one or more core arrays, respective input/output (I/O) circuitry for each of the one or more core arrays, and control circuitry coupled to the first and second word-line decoder circuitries, the one or more core arrays, and the respective I/O circuitries. Also, one or more control signals, activated from one or more control signals generated in the control circuitry, may be configured to select corresponding one or more core arrays of the one or more core arrays.

公开(公告)号：US10665591B2

公开(公告)日：2020-05-26

申请号：US16122752

申请日：2018-09-05

Applicant: Arm Limited

Inventor： Yew Keong Chong ,  Sriram Thyagarajan ,  Kumaraswamy Ramanathan ,  Damayanti Datta

IPC: H01L27/092 ,  H01L29/78 ,  H01L21/8238 ,  G11C11/40 ,  H03K3/012

Abstract: Briefly, embodiments of claimed subject matter relate to devices and methods for modifying, such as decreasing rise time and/or fall time, of a driver signal output. To achieve such modifications in driver output signals, additional gates may be positioned at PMOS and/or NMOS regions of a semiconductor film. In addition, at least in particular embodiments, etching of portions of one or more semiconductor regions may increase compressive or tensile stress, which may further operate to modify driver output signals.

公开(公告)号：US20200075591A1

公开(公告)日：2020-03-05

申请号：US16122752

申请日：2018-09-05

Applicant: Arm Limited

Inventor： Yew Keong Chong ,  Sriram Thyagarajan ,  Kumaraswamy Ramanathan ,  Damayanti Datta

IPC: H01L27/092 ,  H01L29/78 ,  H03K3/012 ,  G11C11/40 ,  H01L21/8238

Abstract: Briefly, embodiments of claimed subject matter relate to devices and methods for modifying, such as decreasing rise time and/or fall time, of a driver signal output. To achieve such modifications in driver output signals, additional gates may be positioned at PMOS and/or NMOS regions of a semiconductor film. In addition, at least in particular embodiments, etching of portions of one or more semiconductor regions may increase compressive or tensile stress, which may further operate to modify driver output signals.

公开(公告)号：US20190325950A1

公开(公告)日：2019-10-24

申请号：US15961862

申请日：2018-04-24

Applicant: Arm Limited

Inventor： Yew Keong Chong ,  Andy Wangkun Chen ,  Sriram Thyagarajan

IPC: G11C11/419 ,  G11C11/418

Abstract: Various implementations described herein are directed to an integrated circuit having multiple bitcell arrays and multiple input ports including a single write input port for the multiple bitcell arrays and multiple read input ports for the multiple bitcell arrays. The integrated circuit may include multiple read output ports for the multiple bitcell arrays. The single write input port is used for writing data to the multiple bitcell arrays, and the multiple read input ports are used separately for reading data from the multiple bitcell arrays for output to the multiple read output ports.

公开(公告)号：US20190026417A1

公开(公告)日：2019-01-24

申请号：US16140461

申请日：2018-09-24

Applicant: Arm Limited

Inventor： Paul de Dood ,  Marlin Wayne Frederick, JR. ,  Jerry Chaoyuan Wang ,  Brian Tracy Cline ,  Xiaoqing Xu ,  Andy Wangkun Chen ,  Yew Keong Chong ,  Tom Shore ,  Sriram Thyagarajan ,  Gus Yeung ,  Daniel J. Albers ,  David William Granda

IPC: G06F17/50

Abstract: A computer implemented system and method is provided for generating a layout of the cell defining a circuit component, the layout providing a layout pattern for a target process technology. The method comprises obtaining an archetype layout providing a valid layout pattern for the cell having regard to design rules of the target process technology, and receiving an input data file providing a process technology independent schematic of the circuit component for which the cell is to be generated. A schematic sizing operation is then performed on the input data file, having regard to both schematic constraints applicable to the target process technology and layout constraints derived from the archetype layout, in order to generate an output data file providing a process technology dependent schematic of the circuit component. A cell generation operation is then performed using the output data file and layout data determined from the archetype layout in order to generate the layout of the cell. Such an approach enables both the schematic and layout to be co-optimised during generation of the layout of the cell.

公开(公告)号：US20170117022A1

公开(公告)日：2017-04-27

申请号：US15401588

申请日：2017-01-09

Applicant: ARM Limited

Inventor： Yew Keong Chong ,  Andy Wangkun Chen ,  Sriram Thyagarajan ,  Gus Yeung ,  James Dennis Dodrill

IPC: G11C7/10 ,  G11C29/50 ,  G11C7/20

CPC classification number: G11C7/1012 ,  G11C5/141 ,  G11C8/06 ,  G11C8/18 ,  G11C29/022 ,  G11C29/023 ,  G11C29/025 ,  G11C29/028 ,  G11C29/50012 ,  G11C29/702

Abstract: Various implementations described herein are directed to a method of integrated circuit design and fabrication. In the implementation of a memory integrated circuit, the floorplan of the integrated circuit comprises memory blocks, where instantiations of the memory blocks are optimized to satisfy timing specifications while minimizing power consumption or not significantly contributing to leakage current.