公开(公告)号：US20180024781A1

公开(公告)日：2018-01-25

申请号：US15385810

申请日：2016-12-20

Applicant: Atmel Corporation

Inventor： Frode Milch Pedersen ,  Ian Fullerton ,  Joseph Martinez ,  Martin Olsson

IPC: G06F3/06

CPC classification number: G06F3/0679 ,  G06F3/062 ,  G06F3/0655 ,  G06F12/0246 ,  G06F2212/1052 ,  G06F2212/72 ,  G06F2212/7201

Abstract: The disclosed embodiments provide security extensions for memory (e.g., non-volatile memory) by means of address and data scrambling and differential data storage to minimize exposure to side channel attacks and obfuscate the stored data. The scrambling function maximizes reverse engineering costs when recovering sequences of secret keys.

公开(公告)号：US09405720B2

公开(公告)日：2016-08-02

申请号：US13941671

申请日：2013-07-15

Applicant: Atmel Corporation

Inventor： Frode Milch Pedersen ,  Sebastien Jouin ,  Ian Fullerton

IPC: G06F13/42 ,  G06F13/16

CPC classification number: G06F3/0611 ,  G06F3/0655 ,  G06F3/0679 ,  G06F13/1689 ,  G06F13/4217 ,  G06F13/4243 ,  Y02D10/14 ,  Y02D10/151

Abstract: A latch signal is received from a non-volatile memory device that is indicative of a current access time for the non-volatile memory device. The access time represents an amount of time required for the non-volatile memory device to make data available responsive to a request for data. A bus system clock signal is received. The latch signal is evaluated and a wait state for the non-volatile memory device is adjusted based on the evaluation. The wait state represents a number of cycles of the bus system clock used by a central processing unit for an access of the non-volatile memory device. A bus system data ready signal that is triggered based on the adjusted wait state is produced. The bus system data ready signal, when triggered, indicates that data is available responsive to the request.

Abstract translation: 从非易失性存储器件接收指示非易失性存储器件的当前访问时间的锁存信号。 访问时间表示非易失性存储器件根据数据请求使数据可用的时间量。 接收总线系统时钟信号。 评估锁存信号，并且基于评估来调整非易失性存储器件的等待状态。 等待状态表示由中央处理单元用于访问非易失性存储器件的总线系统时钟的周期数。 产生基于调整后的等待状态触发的总线系统数据就绪信号。 当触发时，总线系统数据就绪信号表示响应于该请求可用数据。

公开(公告)号：US09054685B2

公开(公告)日：2015-06-09

申请号：US13873013

申请日：2013-04-29

Applicant: Atmel Corporation

Inventor： Morten Lund ,  Ian Fullerton

IPC: H03H11/26 ,  H03K5/13

CPC classification number: H03K5/131 ,  G06F13/4291

Abstract: A circuit is disclosed that provides a programmable hold time for a bus signal without running a system clock and without a frequency requirement between the system clock and a bus clock.

Abstract translation: 公开了一种电路，其提供总线信号的可编程保持时间，而不运行系统时钟，并且在系统时钟和总线时钟之间没有频率要求。