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    MEMORY CONTROLLER WITH ENHANCED LOW-POWER STATE
    11.
    发明申请
    MEMORY CONTROLLER WITH ENHANCED LOW-POWER STATE 有权

    公开(公告)号：US20250004651A1

    公开(公告)日：2025-01-02

    申请号：US18216109

    申请日：2023-06-29

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Kevin M. Brandl ,  Jean J. Chittilappilly ,  Tahsin Askar ,  James R. Magro

    IPC: G06F3/06

    Abstract: A memory accessing circuit includes a memory controller for scheduling accesses to a memory, and a physical interface circuit for driving signals to the memory according to scheduled accesses and having configuration data. The memory controller comprises a memory and is responsive to a low power mode entry signal to save the configuration data in the memory. The physical interface circuit removes operating power from circuitry in the physical interface circuit that stores the configuration data in response to the memory controller completing a save operation.

    Signalling for heterogeneous memory systems
    14.
    发明授权
    Signalling for heterogeneous memory systems 有权

    公开(公告)号：US11748034B2

    公开(公告)日：2023-09-05

    申请号：US17409099

    申请日：2021-08-23

    Applicant: Advanced Micro Devices, Inc.

    Inventor： James R. Magro ,  Kedarnath Balakrishnan

    IPC: G06F3/00 ,  G06F3/06

    CPC classification number: G06F3/0659 ,  G06F3/0611 ,  G06F3/0679

    Abstract: A memory controller selects from among a plurality of memory access commands including volatile memory reads, volatile memory writes, non-volatile memory reads, and non-volatile memory writes. The selected memory access commands are transmitted to a heterogenous memory channel coupled to a non-volatile memory and a volatile memory. The non-volatile read commands that are transmitted are stored in a non-volatile command queue (NV queue). A ready response is received from the non-volatile memory indicating that responsive data is available for an associated one of the non-volatile read commands. In response to receiving the ready response, a send command is transmitted for commanding the non-volatile memory to send the responsive data.

    ERROR RECOVERY FOR NON-VOLATILE MEMORY MODULES
    15.
    发明申请
    ERROR RECOVERY FOR NON-VOLATILE MEMORY MODULES 有权

    公开(公告)号：US20230125792A1

    公开(公告)日：2023-04-27

    申请号：US18084350

    申请日：2022-12-19

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Jing Wang ,  James R. Magro ,  Kedarnath Balakrishnan

    IPC: G06F11/14 ,  G06F3/06

    Abstract: A memory controller includes a command queue, a memory interface queue, at least one storage queue, and a replay control circuit. The command queue has a first input for receiving memory access commands. The memory interface queue receives commands selected from the command queue and couples to a heterogeneous memory channel which is coupled to at least one non-volatile storage class memory (SCM) module. The at least one storage queue stores memory access commands that are placed in the memory interface queue. The replay control circuit detects that an error has occurred requiring a recovery sequence, and in response to the error, initiates the recovery sequence. In the recovery sequence, the replay control circuit transmits selected memory access commands from the at least one storage queue by grouping non-volatile read commands together separately from all pending volatile reads, volatile writes, and non-volatile writes.

    Command replay for non-volatile dual inline memory modules
    18.
    发明授权
    Command replay for non-volatile dual inline memory modules 有权

    公开(公告)号：US11137941B2

    公开(公告)日：2021-10-05

    申请号：US16730092

    申请日：2019-12-30

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Jing Wang ,  James R. Magro ,  Kedarnath Balakrishnan

    IPC: G06F3/06

    Abstract: Memory access commands are placed in a memory interface queue and transmitted from the memory interface queue to a heterogeneous memory channel coupled to a volatile dual in-line memory module (DIMM) and a non-volatile DIMM. Selected memory access commands that are placed in the memory interface queue are stored in a replay queue. The non-volatile reads that are placed in the memory interface queue are in a non-volatile command queue (NV queue). The method detects, based on information received over the heterogeneous memory channel, that an error has occurred requiring a recovery sequence. In response to the error, the method initiates the recovery sequence including (i) transmitting selected memory access commands that are stored in the replay queue, and (ii) transmitting non-volatile reads that are stored in the NV queue.

    Low power memory throttling
    19.
    发明授权
    Low power memory throttling 有权

    公开(公告)号：US10198216B2

    公开(公告)日：2019-02-05

    申请号：US15168043

    申请日：2016-05-28

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Kedarnath Balakrishnan ,  Kevin M. Brandl ,  James R. Magro

    IPC: G06F3/06 ,  G06F13/16 ,  G11C7/04 ,  G11C11/406 ,  G11C11/4072

    Abstract: In one form, a data processing system includes a memory channel having a plurality of ranks, and a data processor. The data processor is coupled to the memory channel and is adapted to access each of the plurality of ranks. In response to detecting a predetermined event, the data processor selects an active rank of the plurality of ranks and places other ranks besides the active rank in a low power state, wherein the other ranks include at least one rank with a pending request at a time of detection of the predetermined event. The data processor subsequently processes a memory access request to the active rank.

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