公开(公告)号：US11636054B2

公开(公告)日：2023-04-25

申请号：US17219273

申请日：2021-03-31

Applicant: Advanced Micro Devices, Inc.

Inventor： Kevin M. Brandl ,  Indrani Paul ,  Jean J. Chittilappilly ,  Abhishek Kumar Verma ,  James R. Magro ,  Kavyashree Pilar

IPC: G06F1/3234 ,  G06F13/16 ,  G11C11/406 ,  G06F1/3296 ,  G06F3/06

Abstract: A memory controller includes a command queue and an arbiter operating in a first voltage domain, and a physical layer interface (PHY) operating in a second voltage domain. The memory controller includes isolation cells operable to isolate the PHY from the first voltage domain. A local power state controller, in response to a first power state command, provides configuration and state data for storage in an on-chip RAM memory, causes the memory controller to enter a powered-down state, and maintains the PHY in a low-power state in which the second voltage domain is powered while the memory controller is in the powered-down state.

公开(公告)号：US20250110663A1

公开(公告)日：2025-04-03

申请号：US18375030

申请日：2023-09-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Jean J. Chittilappilly ,  Kevin M. Brandl ,  Jing Wang ,  Kedarnath Balakrishnan

IPC: G06F3/06

Abstract: A data processor that is operable to be coupled to a memory includes a memory operation array, a controller, a refresh logic circuit, and a selector. The memory operation array is for storing memory operations for a first power state of the memory. The controller is responsive to a power state change request to execute a plurality of memory operations from the memory operation array when the first power state is selected. The refresh logic circuit generates refresh cycles periodically for the memory. The selector is for multiplexing the refresh cycles with the memory operations during a power state change to the first power state.

公开(公告)号：US20250004651A1

公开(公告)日：2025-01-02

申请号：US18216109

申请日：2023-06-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Kevin M. Brandl ,  Jean J. Chittilappilly ,  Tahsin Askar ,  James R. Magro

IPC: G06F3/06

Abstract: A memory accessing circuit includes a memory controller for scheduling accesses to a memory, and a physical interface circuit for driving signals to the memory according to scheduled accesses and having configuration data. The memory controller comprises a memory and is responsive to a low power mode entry signal to save the configuration data in the memory. The physical interface circuit removes operating power from circuitry in the physical interface circuit that stores the configuration data in response to the memory controller completing a save operation.

公开(公告)号：US12265732B1

公开(公告)日：2025-04-01

申请号：US18375030

申请日：2023-09-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Jean J. Chittilappilly ,  Kevin M. Brandl ,  Jing Wang ,  Kedarnath Balakrishnan

IPC: G06F3/06

Abstract: A data processor that is operable to be coupled to a memory includes a memory operation array, a controller, a refresh logic circuit, and a selector. The memory operation array is for storing memory operations for a first power state of the memory. The controller is responsive to a power state change request to execute a plurality of memory operations from the memory operation array when the first power state is selected. The refresh logic circuit generates refresh cycles periodically for the memory. The selector is for multiplexing the refresh cycles with the memory operations during a power state change to the first power state.

公开(公告)号：US20240004560A1

公开(公告)日：2024-01-04

申请号：US17853393

申请日：2022-06-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Jean J. Chittilappilly ,  Kevin M. Brandl ,  Michael L. Choate

IPC: G06F3/06

CPC classification number: G06F3/0625 ,  G06F3/0659 ,  G06F3/0673

Abstract: A data processor is adapted to couple to a memory. The data processor includes a memory operation array, a power engine, and an initialization circuit. The memory operation array includes a command portion and a data portion. The power engine has an input for receiving power state change request signals and an output for providing memory operations responsive to instructions stored in the command portion. The initialization circuit populates the data portion such that consecutive memory operations are separated by an amount corresponding to a predetermined minimum timing parameter.

公开(公告)号：US20220318161A1

公开(公告)日：2022-10-06

申请号：US17219273

申请日：2021-03-31

Applicant: Advanced Micro Devices, Inc.

Inventor： Kevin M. Brandl ,  Indrani Paul ,  Jean J. Chittilappilly ,  Abhishek Kumar Verma ,  James R. Magro ,  Kavyashree Pilar

IPC: G06F13/16 ,  G06F1/3234 ,  G06F1/3296 ,  G11C11/406

Abstract: A memory controller includes a command queue and an arbiter operating in a first voltage domain, and a physical layer interface (PHY) operating in a second voltage domain. The memory controller includes isolation cells operable to isolate the PHY from the first voltage domain. A local power state controller, in response to a first power state command, provides configuration and state data for storage in an on-chip RAM memory, causes the memory controller to enter a powered-down state, and maintains the PHY in a low-power state in which the second voltage domain is powered while the memory controller is in the powered-down state.