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    Periodic receiver clock data recovery with dynamic data edge
    16.
    发明授权
    Periodic receiver clock data recovery with dynamic data edge 有权

    公开(公告)号：US12174769B2

    公开(公告)日：2024-12-24

    申请号：US17705048

    申请日：2022-03-25

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Gurunath Dollin ,  Edoardo Prete ,  Milam Paraschou ,  Edward Wade Thoenes ,  Ryan J. Hensley ,  Gerald R. Talbot

    IPC: G06F13/40 ,  G06F1/08 ,  G06F1/12 ,  G06F13/42 ,  H03K19/173

    Abstract: Systems, apparatuses, and methods for implementing a periodic receiver clock data recovery scheme with dynamic data edge paths are disclosed. An IQ link calibration scheme performs a non-destructive data and edge path switch to determine an IQ offset without disturbing the data. A data path and an edge path pass through multiple stages of deserializers to widen the data path, with the deserializers clocked by clock divided versions of the original data and edge clocks. To initiate a calibration routine, the edge clock is aligned with the data clock, and then data and edge paths are swapped at a common point in a slower clock domain. The data path is then calibrated while the edge path carries the data signal. After the data path is calibrated, the edge and data paths are swapped back to the original configuration.

    SENSE AMPLIFIER WITH INCREASED HEADROOM
    17.
    发明申请
    SENSE AMPLIFIER WITH INCREASED HEADROOM 有权

    公开(公告)号：US20210090615A1

    公开(公告)日：2021-03-25

    申请号：US17113346

    申请日：2020-12-07

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Milam Paraschou ,  Jeffrey Cooper

    IPC: G11C7/06 ,  G11C15/04

    Abstract: Systems, apparatuses, and methods for implementing a sampling circuit with increased headroom are disclosed. A sampling circuit includes at least a pair of input signal transistors connected via their drains to a cross-coupled pair of state nodes. The cross-coupled pair of state nodes are coupled to a tail transistor device via the sources of N-type transistors. When clock goes low, the circuit precharges the cross-coupled pair of state nodes while simultaneously attempting to amplify the difference between the pair of input signals. The amplification is performed by a pair of transistors in series between a source of each input signal transistor and ground. Each gate of the pair of transistors is connected to an inverted clock signal. When clock goes high, the circuit stops precharging and a voltage difference between the pair of input signals is regenerated to create a resulting differential voltage on the pair of state nodes.

    Sense amplifier with increased headroom
    18.
    发明授权
    Sense amplifier with increased headroom 有权

    公开(公告)号：US10861507B2

    公开(公告)日：2020-12-08

    申请号：US16368311

    申请日：2019-03-28

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Milam Paraschou ,  Jeffrey Cooper

    IPC: G11C7/06 ,  G11C15/04

    Abstract: Systems, apparatuses, and methods for implementing a sampling circuit with increased headroom are disclosed. A sampling circuit includes at least a pair of input signal transistors connected via their drains to a cross-coupled pair of state nodes. The cross-coupled pair of state nodes are coupled to a tail transistor device via the sources of N-type transistors. When clock goes low, the circuit precharges the cross-coupled pair of state nodes while simultaneously attempting to amplify the difference between the pair of input signals. The amplification is performed by a pair of transistors in series between a source of each input signal transistor and ground. Each gate of the pair of transistors is connected to an inverted clock signal. When clock goes high, the circuit stops precharging and a voltage difference between the pair of input signals is regenerated to create a resulting differential voltage on the pair of state nodes.

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