公开(公告)号：US20240329846A1

公开(公告)日：2024-10-03

申请号：US18129390

申请日：2023-03-31

Applicant: Advanced Micro Devices, Inc.

Inventor： Vignesh Adhinarayanan ,  Michael Ignatowski ,  Hyung-Dong Lee

IPC: G06F3/06

CPC classification number: G06F3/0613 ,  G06F3/0634 ,  G06F3/0673

Abstract: A memory sprint controller, responsive to an indicator of an irregular memory access phase, causes a memory controller to enter a sprint mode in which it temporarily adjusts at least one timing parameter of a dynamic random access memory (DRAM) to reduce a time in which a designated number of activate (ACT) commands are allowed to be dispatched to the DRAM.

公开(公告)号：US12086418B1

公开(公告)日：2024-09-10

申请号：US18129436

申请日：2023-03-31

Applicant: Advanced Micro Devices, Inc.

Inventor： Vignesh Adhinarayanan ,  Michael Ignatowski ,  Hyung-Dong Lee

IPC: G06F3/06

CPC classification number: G06F3/0613 ,  G06F3/0634 ,  G06F3/0673

Abstract: A memory sprint controller, responsive to an indicator of an irregular memory access phase, causes a memory controller to enter a sprint mode in which it temporarily adjusts at least one timing parameter of a dynamic random access memory (DRAM) to reduce a time in which a designated number of activate (ACT) commands are allowed to be dispatched to the DRAM.

公开(公告)号：US11756606B2

公开(公告)日：2023-09-12

申请号：US17549359

申请日：2021-12-13

Applicant: Advanced Micro Devices, Inc.

Inventor： Sriseshan Srikanth ,  Vignesh Adhinarayanan ,  Jagadish B. Kotra ,  Sergey Blagodurov

IPC: G11C11/4093 ,  G11C11/4096 ,  H03K19/17728 ,  G11C8/18 ,  H03K19/173 ,  G11C11/408

CPC classification number: G11C11/4093 ,  G11C8/18 ,  G11C11/4087 ,  G11C11/4096 ,  H03K19/1737 ,  H03K19/17728

Abstract: A fine-grained dynamic random-access memory (DRAM) includes a first memory bank, a second memory bank, and a dual mode I/O circuit. The first memory bank includes a memory array divided into a plurality of grains, each grain including a row buffer and input/output (I/O) circuitry. The dual-mode I/O circuit is coupled to the I/O circuitry of each grain in the first memory bank, and operates in a first mode in which commands having a first data width are routed to and fulfilled individually at each grain, and a second mode in which commands having a second data width different from the first data width are fulfilled by at least two of the grains in parallel.

公开(公告)号：US20230186976A1

公开(公告)日：2023-06-15

申请号：US17549359

申请日：2021-12-13

Applicant: Advanced Micro Devices, Inc.

Inventor： Sriseshan Srikanth ,  Vignesh Adhinarayanan ,  Jagadish B. Kotra ,  Sergey Blagodurov

IPC: G11C11/4093 ,  G11C11/4096 ,  G11C11/408 ,  G11C8/18 ,  H03K19/173 ,  H03K19/17728

CPC classification number: G11C11/4093 ,  G11C11/4096 ,  G11C11/4087 ,  G11C8/18 ,  H03K19/1737 ,  H03K19/17728

Abstract: A fine-grained dynamic random-access memory (DRAM) includes a first memory bank, a second memory bank, and a dual mode I/O circuit. The first memory bank includes a memory array divided into a plurality of grains, each grain including a row buffer and input/output (I/O) circuitry. The dual-mode I/O circuit is coupled to the I/O circuitry of each grain in the first memory bank, and operates in a first mode in which commands having a first data width are routed to and fulfilled individually at each grain, and a second mode in which commands having a second data width different from the first data width are fulfilled by at least two of the grains in parallel.

公开(公告)号：US20220100257A1

公开(公告)日：2022-03-31

申请号：US17033000

申请日：2020-09-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Vedula Venkata Srikant Bharadwaj ,  Shomit N. Das ,  Anthony T. Gutierrez ,  Vignesh Adhinarayanan

IPC: G06F1/3287 ,  G06F1/324 ,  G06F1/3296 ,  G06F9/50

Abstract: Systems, methods, devices, and computer-implemented instructions for processor power management implemented in a compiler. In some implementations, a characteristic of code is determined. An instruction based on the determined characteristic is inserted into the code. The code and inserted instruction are compiled to generate compiled code. The compiled code is output.