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    Pairing SIMD lanes to perform double precision operations
    11.
    发明授权
    Pairing SIMD lanes to perform double precision operations 有权

    公开(公告)号：US11409536B2

    公开(公告)日：2022-08-09

    申请号：US15342809

    申请日：2016-11-03

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Bin He ,  YunXiao Zou ,  Jiasheng Chen ,  Michael Mantor

    IPC: G06F9/38 ,  G06F9/30

    Abstract: A method and apparatus for performing a multi-precision computation in a plurality of arithmetic logic units (ALUs) includes pairing a first Single Instruction/Multiple Data (SIMD) block channel device with a second SIMD block channel device to create a first block pair having one-level staggering between the first and second channel devices. A third SIMD block channel device is paired with a fourth SIMD block channel device to create a second block pair having one-level staggering between the third and fourth channel devices. A plurality of source inputs are received at the first block pair and the second block pair. The first block pair computes a first result, and the second block pair computes a second result.

    STREAM PROCESSOR WITH OVERLAPPING EXECUTION
    12.
    发明申请
    STREAM PROCESSOR WITH OVERLAPPING EXECUTION 审中-公开

    公开(公告)号：US20190004807A1

    公开(公告)日：2019-01-03

    申请号：US15657478

    申请日：2017-07-24

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Jiasheng Chen ,  Qingcheng Wang ,  Yunxiao Zou ,  Bin He ,  Jian Yang ,  Michael J. Mantor ,  Brian D. Emberling

    IPC: G06F9/38

    Abstract: Systems, apparatuses, and methods for implementing a stream processor with overlapping execution are disclosed. In one embodiment, a system includes at least a parallel processing unit with a plurality of execution pipelines. The processing throughput of the parallel processing unit is increased by overlapping execution of multi-pass instructions with single pass instructions without increasing the instruction issue rate. A first plurality of operands of a first vector instruction are read from a shared vector register file in a single clock cycle and stored in temporary storage. The first plurality of operands are accessed and utilized to initiate multiple instructions on individual vector elements on a first execution pipeline in subsequent clock cycles. A second plurality of operands are read from the shared vector register file during the subsequent clock cycles to initiate execution of one or more second vector instructions on the second execution pipeline.

    Processing unit with small footprint arithmetic logic unit
    15.
    发明授权
    Processing unit with small footprint arithmetic logic unit 有权

    公开(公告)号：US12217021B2

    公开(公告)日：2025-02-04

    申请号：US18219268

    申请日：2023-07-07

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Bin He ,  Shubh Shah ,  Michael Mantor

    IPC: G06F7/57 ,  G06F17/16 ,  G06N3/08

    Abstract: A parallel processing unit employs an arithmetic logic unit (ALU) having a relatively small footprint, thereby reducing the overall power consumption and circuit area of the processing unit. To support the smaller footprint, the ALU includes multiple stages to execute operations corresponding to a received instruction. The ALU executes at least one operation at a precision indicated by the received instruction, and then reduces the resulting data of the at least one operation to a smaller size before providing the results to another stage of the ALU to continue execution of the instruction.

    DUAL VECTOR ARITHMETIC LOGIC UNIT
    17.
    发明申请
    DUAL VECTOR ARITHMETIC LOGIC UNIT 有权

    公开(公告)号：US20220188076A1

    公开(公告)日：2022-06-16

    申请号：US17121354

    申请日：2020-12-14

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Bin He ,  Brian Emberling ,  Mark Leather ,  Michael Mantor

    IPC: G06F7/57 ,  G06F17/16 ,  G06F9/38 ,  G06T1/20

    Abstract: A processing system executes wavefronts at multiple arithmetic logic unit (ALU) pipelines of a single instruction multiple data (SIMD) unit in a single execution cycle. The ALU pipelines each include a number of ALUs that execute instructions on wavefront operands that are collected from vector general process register (VGPR) banks at a cache and output results of the instructions executed on the wavefronts at a buffer. By storing wavefronts supplied by the VGPR banks at the cache, a greater number of wavefronts can be made available to the SIMD unit without increasing the VGPR bandwidth, enabling multiple ALU pipelines to execute instructions during a single execution cycle.

    Dual vector arithmetic logic unit
    19.
    发明授权
    Dual vector arithmetic logic unit 有权

    公开(公告)号：US12299413B2

    公开(公告)日：2025-05-13

    申请号：US18414164

    申请日：2024-01-16

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Bin He ,  Brian Emberling ,  Mark Leather ,  Michael Mantor

    IPC: G06F7/57 ,  G06F9/38 ,  G06F17/16 ,  G06T1/20 ,  G06F15/80

    Abstract: A processing system executes wavefronts at multiple arithmetic logic unit (ALU) pipelines of a single instruction multiple data (SIMD) unit in a single execution cycle. The ALU pipelines each include a number of ALUs that execute instructions on wavefront operands that are collected from vector general process register (VGPR) banks at a cache and output results of the instructions executed on the wavefronts at a buffer. By storing wavefronts supplied by the VGPR banks at the cache, a greater number of wavefronts can be made available to the SIMD unit without increasing the VGPR bandwidth, enabling multiple ALU pipelines to execute instructions during a single execution cycle.

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