公开(公告)号：US20230195642A1

公开(公告)日：2023-06-22

申请号：US17556257

申请日：2021-12-20

Applicant: Advanced Micro Devices, Inc.

Inventor： Vydhyanathan Kalyanasundharam ,  John Wuu ,  Chintan S. Patel

IPC: G06F12/0895 ,  G06F12/0811 ,  G06F12/0891 ,  G06F13/16

CPC classification number: G06F12/0895 ,  G06F12/0811 ,  G06F12/0891 ,  G06F13/1668

Abstract: A cache includes an upstream port, a cache memory for storing cache lines each having a line width, and a cache controller. The cache controller is coupled to the upstream port and the cache memory. The upstream port transfers data words having a transfer width less than the line width. In response to a cache line fill, the cache controller selectively determines data bus inversion information for a sequence of data words having the transfer width, and stores the data bus inversion information along with selected inverted data words for the cache line fill in the cache memory.

公开(公告)号：US20210406177A1

公开(公告)日：2021-12-30

申请号：US17033287

申请日：2020-09-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Chintan S. Patel ,  Vydhyanathan Kalyanasundharam ,  Benjamin Tsien

IPC: G06F12/0817

Abstract: A method of controlling a cache is disclosed. The method comprises receiving a request to allocate a portion of memory to store data. The method also comprises directly mapping a portion of memory to an assigned contiguous portion of the cache memory when the request to allocate a portion of memory to store the data includes a cache residency request that the data continuously resides in cache memory. The method also comprises mapping the portion of memory to the cache memory using associative mapping when the request to allocate a portion of memory to store the data does not include a cache residency request that data continuously resides in the cache memory.

公开(公告)号：US10861504B2

公开(公告)日：2020-12-08

申请号：US15725912

申请日：2017-10-05

Applicant: Advanced Micro Devices, Inc.

Inventor： Benjamin Tsien ,  Alexander J. Branover ,  Alan Dodson Smith ,  Chintan S. Patel

IPC: G11C5/06 ,  G06F1/3296 ,  G06F13/40 ,  G06F1/3234 ,  G06F1/3203 ,  G06F1/3287 ,  G11C5/02 ,  G11C5/14

Abstract: Systems, apparatuses, and methods for implementing dynamic control of a multi-region fabric are disclosed. A system includes at least one or more processing units, one or more memory devices, and a communication fabric coupled to the processing unit(s) and memory device(s). The system partitions the fabric into multiple regions based on different traffic types and/or periodicities of the clients connected to the regions. For example, the system partitions the fabric into a stutter region for predictable, periodic clients and a non-stutter region for unpredictable, non-periodic clients. The system power-gates the entirety of the fabric in response to detecting a low activity condition. After power-gating the entirety of the fabric, the system periodically wakes up one or more stutter regions while keeping the other non-stutter regions in power-gated mode. Each stutter region monitors stutter client(s) for activity and processes any requests before going back into power-gated mode.

公开(公告)号：US10403351B1

公开(公告)日：2019-09-03

申请号：US15902580

申请日：2018-02-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Benjamin Tsien ,  Chintan S. Patel ,  Vamsi Krishna Alla ,  Alan Dodson Smith

IPC: G11C7/00 ,  G11C11/406 ,  G06F13/16

Abstract: Systems, apparatuses, and methods for using a scoreboard to track updates to configuration state registers are disclosed. A system includes one or more processing nodes, one or more memory devices, a plurality of configuration state registers, and a communication fabric coupled to the processing unit(s) and memory device(s). The system uses a scoreboard to track updates to the configuration state registers during run-time. Prior to a node going into a power-gated state, the system stores only those configuration state registers that have changed. This reduces the amount of data written to memory on each transition into power-gated state, and increases the amount of time the node can spend in the power-gated state. Also, configuration state registers are grouped together to match the memory access granularity, and each group of configuration state registers has a corresponding scoreboard entry.

公开(公告)号：US20230418753A1

公开(公告)日：2023-12-28

申请号：US17852296

申请日：2022-06-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Chintan S. Patel ,  Alexander J. Branover ,  Benjamin Tsien ,  Edgar Munoz ,  Vydhyanathan Kalyanasundharam

IPC: G06F12/0871 ,  G06F12/0864 ,  G06F12/0811

CPC classification number: G06F12/0871 ,  G06F12/0811 ,  G06F12/0864

Abstract: A technique for operating a cache is disclosed. The technique includes based on a workload change, identifying a first allocation permissions policy; operating the cache according to the first allocation permissions policy; based on set sampling, identifying a second allocation permissions policy; and operating the cache according to the second allocation permissions policy.

公开(公告)号：US20230418745A1

公开(公告)日：2023-12-28

申请号：US17852300

申请日：2022-06-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Chintan S. Patel ,  Vydhyanathan Kalyanasundharam ,  Benjamin Tsien ,  Alexander J. Branover

IPC: G06F12/0802

CPC classification number: G06F12/0802 ,  G06F2212/60

Abstract: A technique for operating a cache is disclosed. The technique includes utilizing a first portion of a cache in a directly accessed manner; and utilizing a second portion of the cache as a cache.

公开(公告)号：US11822484B2

公开(公告)日：2023-11-21

申请号：US17556257

申请日：2021-12-20

Applicant: Advanced Micro Devices, Inc.

Inventor： Vydhyanathan Kalyanasundharam ,  John Wuu ,  Chintan S. Patel

IPC: G06F12/08 ,  G06F12/0895 ,  G06F13/16 ,  G06F12/0891 ,  G06F12/0811

CPC classification number: G06F12/0895 ,  G06F12/0811 ,  G06F12/0891 ,  G06F13/1668

Abstract: A cache includes an upstream port, a cache memory for storing cache lines each having a line width, and a cache controller. The cache controller is coupled to the upstream port and the cache memory. The upstream port transfers data words having a transfer width less than the line width. In response to a cache line fill, the cache controller selectively determines data bus inversion information for a sequence of data words having the transfer width, and stores the data bus inversion information along with selected inverted data words for the cache line fill in the cache memory.

公开(公告)号：US11422935B2

公开(公告)日：2022-08-23

申请号：US17033287

申请日：2020-09-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Chintan S. Patel ,  Vydhyanathan Kalyanasundharam ,  Benjamin Tsien

IPC: G06F12/0817

Abstract: A method of controlling a cache is disclosed. The method comprises receiving a request to allocate a portion of memory to store data. The method also comprises directly mapping a portion of memory to an assigned contiguous portion of the cache memory when the request to allocate a portion of memory to store the data includes a cache residency request that the data continuously resides in cache memory. The method also comprises mapping the portion of memory to the cache memory using associative mapping when the request to allocate a portion of memory to store the data does not include a cache residency request that data continuously resides in the cache memory.

公开(公告)号：US11289131B2

公开(公告)日：2022-03-29

申请号：US17113322

申请日：2020-12-07

Applicant: Advanced Micro Devices, Inc.

Inventor： Benjamin Tsien ,  Alexander J. Branover ,  Alan Dodson Smith ,  Chintan S. Patel

IPC: G11C5/06 ,  G06F1/3296 ,  G06F13/40 ,  G06F1/3234 ,  G06F1/3203 ,  G06F1/3287 ,  G11C5/02 ,  G11C5/14

Abstract: Systems, apparatuses, and methods for implementing dynamic control of a multi-region fabric are disclosed. A system includes at least one or more processing units, one or more memory devices, and a communication fabric coupled to the processing unit(s) and memory device(s). The system partitions the fabric into multiple regions based on different traffic types and/or periodicities of the clients connected to the regions. For example, the system partitions the fabric into a stutter region for predictable, periodic clients and a non-stutter region for unpredictable, non-periodic clients. The system power-gates the entirety of the fabric in response to detecting a low activity condition. After power-gating the entirety of the fabric, the system periodically wakes up one or more stutter regions while keeping the other non-stutter regions in power-gated mode. Each stutter region monitors stutter client(s) for activity and processes any requests before going back into power-gated mode.

公开(公告)号：US10608943B2

公开(公告)日：2020-03-31

申请号：US15796528

申请日：2017-10-27

Applicant: Advanced Micro Devices, Inc.

Inventor： Alan Dodson Smith ,  Chintan S. Patel ,  Eric Christopher Morton ,  Vydhyanathan Kalyanasundharam ,  Narendra Kamat

IPC: G01R31/08 ,  G06F11/00 ,  G08C15/00 ,  H04J1/16 ,  H04J3/14 ,  H04L1/00 ,  H04L12/26 ,  H04L12/803 ,  G06F9/50 ,  G06F13/36 ,  H04L12/863

Abstract: Systems, apparatuses, and methods for dynamic buffer management in multi-client token flow control routers are disclosed. A system includes at least one or more processing units, a memory, and a communication fabric with a plurality of routers coupled to the processing unit(s) and the memory. A router servicing multiple active clients allocates a first number of tokens to each active client. The first number of tokens is less than a second number of tokens needed to saturate the bandwidth of each client to the router. The router also allocates a third number of tokens to a free pool, with tokens from the free pool being dynamically allocated to different clients. The third number of tokens is equal to the difference between the second number of tokens and the first number of tokens. An advantage of this approach is reducing the amount of buffer space needed at the router.