公开(公告)号：US20160190079A1

公开(公告)日：2016-06-30

申请号：US14586735

申请日：2014-12-30

Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.

Inventor： Guo-Cheng LIAO ,  Chia-Ching CHEN ,  Yi-Chuan DING

IPC: H01L23/00

CPC classification number: H01L24/16 ,  H01L21/486 ,  H01L23/49811 ,  H01L23/49827 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/08238 ,  H01L2224/10175 ,  H01L2224/11436 ,  H01L2224/11462 ,  H01L2224/1161 ,  H01L2224/13008 ,  H01L2224/13021 ,  H01L2224/13026 ,  H01L2224/13027 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13561 ,  H01L2224/13647 ,  H01L2224/16012 ,  H01L2224/16013 ,  H01L2224/16014 ,  H01L2224/16105 ,  H01L2224/16108 ,  H01L2224/16235 ,  H01L2224/16503 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81139 ,  H01L2224/81193 ,  H01L2224/81447 ,  H01L2224/81815 ,  H01L2224/83104 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/014 ,  H01L2924/3841 ,  H05K3/007 ,  H05K3/205 ,  H05K3/4682 ,  H05K2201/09509 ,  H05K2201/10378 ,  H05K2201/10674 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: The present disclosure relates to a semiconductor package structure including a semiconductor substrate, a semiconductor chip and a conductive material. The semiconductor substrate includes an insulating layer, a conductive circuit layer and a conductive bump. The conductive circuit layer is recessed from the top surface of the insulating layer, and includes at least one pad. The conductive bump is disposed on the at least one pad. A side surface of the conductive bump, a top surface of the at least one pad and a side surface of the insulating layer together define an accommodating space. The conductive material is electrically connected the conductive bump and the semiconductor chip, and a portion of the conductive material is disposed in the accommodating space.

Abstract translation: 本公开涉及包括半导体衬底，半导体芯片和导电材料的半导体封装结构。 半导体衬底包括绝缘层，导电电路层和导电凸块。 导电电路层从绝缘层的顶表面凹入，并且包括至少一个焊盘。 导电凸块设置在至少一个垫上。 导电凸块的侧表面，至少一个焊盘的顶表面和绝缘层的侧表面一起限定了容纳空间。 导电材料与导电凸块和半导体芯片电连接，导电材料的一部分设置在容纳空间中。