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    SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME
    13.
    发明申请
    SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME 有权

    公开(公告)号：US20220302004A1

    公开(公告)日：2022-09-22

    申请号：US17205967

    申请日：2021-03-18

    Applicant: Advanced Semiconductor Engineering, Inc.

    Inventor： You-Lung YEN ,  Bernd Karl APPELT

    IPC: H01L23/498 ,  H01L21/48

    Abstract: The present disclosure provides a semiconductor device package. The semiconductor device package includes a substrate having a first surface and a second surface opposite to the first surface of the substrate. The substrate has a through opening extending between the first surface of the substrate and the second surface of the substrate. The semiconductor device package also includes a conductive pad in the through opening and approximal to the second surface of the substrate. The conductive pad has a first surface and a second surface opposite to the first surface of the conductive pad. The semiconductor device package also includes a conductive pillar in contact with the first surface of the conductive pad. The second surface of the conductive pad protrudes from the second surface of the substrate. A method of manufacturing a semiconductor device package is also disclosed.

    PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME
    15.
    发明申请
    PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME 有权

    公开(公告)号：US20210327841A1

    公开(公告)日：2021-10-21

    申请号：US16854730

    申请日：2020-04-21

    Applicant: Advanced Semiconductor Engineering, Inc.

    Inventor： You-Lung YEN ,  Bernd Karl APPELT

    IPC: H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56

    Abstract: A package structure and a manufacturing method are provided. The package structure includes a first circuit layer, a first dielectric layer, an electrical device and a first conductive structure. The first circuit layer includes a first alignment portion. The first dielectric layer covers the first circuit layer. The electrical device is disposed on the first dielectric layer, and includes an electrical contact aligning with the first alignment portion. The first conductive structure extends through the first alignment portion, and electrically connects the electrical contact and the first alignment portion.

    SEMICONDUCTOR PACKAGE AND MANUFACTURING PROCESS
    16.
    发明申请
    SEMICONDUCTOR PACKAGE AND MANUFACTURING PROCESS 有权

    公开(公告)号：US20210225746A1

    公开(公告)日：2021-07-22

    申请号：US17221597

    申请日：2021-04-02

    Applicant: Advanced Semiconductor Engineering, Inc.

    Inventor： Bernd Karl APPELT ,  You-Lung YEN ,  Kay Stefan ESSIG

    IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00

    Abstract: A semiconductor package includes a base material, a capture land, an interconnection structure, a semiconductor chip and an encapsulant. The base material has a top surface and an inner lateral surface. The capture land is disposed in or on the base material, and has an outer side surface. The interconnection structure is disposed along the inner lateral surface of the base material, and on the capture land. The interconnection structure has an outer side surface. An outer side surface of the semiconductor package includes the outer side surface of the capture land and the outer side surface of the interconnection structure. The semiconductor chip is disposed on the top surface of the base material. The encapsulant is disposed adjacent to the top surface of the base material, and covers the semiconductor chip.

    DOUBLE SIDE VIA LAST METHOD FOR DOUBLE EMBEDDED PATTERNED SUBSTRATE
    18.
    发明申请
    DOUBLE SIDE VIA LAST METHOD FOR DOUBLE EMBEDDED PATTERNED SUBSTRATE 有权
    双面嵌入式图案的双面方法

    公开(公告)号：US20160315041A1

    公开(公告)日：2016-10-27

    申请号：US14696355

    申请日：2015-04-24

    Applicant: Advanced Semiconductor Engineering, Inc.

    Inventor： You-Lung YEN ,  Chih-Cheng LEE ,  Yuan-Chang SU

    IPC: H01L23/498 ,  H01L23/544 ,  H01L21/683 ,  H01L23/31 ,  H01L21/48

    CPC classification number: H01L23/49838 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/5385 ,  H01L23/544 ,  H01L23/562 ,  H01L2221/68345 ,  H01L2223/54426 ,  H01L2223/54486 ,  H01L2224/73204

    Abstract: An interposer substrate includes a first circuit pattern embedded at a first surface of a dielectric layer and a second circuit pattern embedded at a second surface of the dielectric layer; a middle patterned conductive layer in the dielectric layer between the first circuit pattern and the second circuit pattern; first conductive vias, where each first conductive via includes a first end adjacent to the first circuit pattern and a second end adjacent to the middle patterned conductive layer, wherein a width of the first end is greater than a width of the second end; second conductive vias, where each second conductive via including a third end adjacent to the second circuit pattern and a fourth end adjacent to the middle patterned conductive layer, wherein a width of the third end is greater than a width of the fourth end.

    Abstract translation: 插入器基板包括嵌入电介质层的第一表面的第一电路图案和嵌入电介质层的第二表面的第二电路图案; 在所述第一电路图案和所述第二电路图案之间的介电层中的中间图案化导电层; 第一导电通孔，其中每个第一导电通孔包括与第一电路图案相邻的第一端和与中间图案化导电层相邻的第二端，其中第一端的宽度大于第二端的宽度; 第二导电通孔，其中每个第二导电通孔包括与第二电路图案相邻的第三端和与中间图案化导电层相邻的第四端，其中第三端的宽度大于第四端的宽度。

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