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    System on a chip comprising an I/O steering engine
    11.
    发明授权
    System on a chip comprising an I/O steering engine 有权
    包括I / O转向引擎的芯片上的系统

    公开(公告)号：US09588921B2

    公开(公告)日：2017-03-07

    申请号：US14623914

    申请日：2015-02-17

    Applicant: Amazon Technologies, Inc.

    Inventor： Mark Bradley Davis ,  David James Borland

    IPC: G06F13/364 ,  G06F13/12 ,  G06F13/00 ,  H04L29/06

    CPC classification number: G06F13/364 ,  G06F13/00 ,  G06F13/122 ,  G06F13/128 ,  H04L63/00

    Abstract: Embodiments of the technology can provide steering of one or more I/O resources to compute subsystems on a system-on chip (SoC). The SoC may include a first I/O subsystem comprising a plurality of first I/O resources and a second I/O subsystem comprising a plurality of second I/O resources. A steering engine may steer at least one of the first I/O resources to either a network compute subsystem or to a server compute subsystem and may steer at least one of the second I/O resources to either the network compute subsystem or to the server compute subsystem.

    Abstract translation: 该技术的实施例可以提供一个或多个I / O资源的转向以在片上系统（SoC）上计算子系统。 SoC可以包括包括多个第一I / O资源的第一I / O子系统和包括多个第二I / O资源的第二I / O子系统。 转向引擎可以将至少一个第一I / O资源引导到网络计算子系统或服务器计算子系统，并且可以将第二I / O资源中的至少一个引导到网络计算子系统或服务器 计算子系统。

    SYSTEM ON A CHIP COMPRISING RECONFIGURABLE RESOURCES FOR MULTIPLE COMPUTE SUB-SYSTEMS
    12.
    发明申请
    SYSTEM ON A CHIP COMPRISING RECONFIGURABLE RESOURCES FOR MULTIPLE COMPUTE SUB-SYSTEMS 审中-公开
    包含多个计算机辅助系统的可重新配置资源的芯片系统

    公开(公告)号：US20160179717A1

    公开(公告)日：2016-06-23

    申请号：US14578010

    申请日：2014-12-19

    Applicant: Amazon Technologies, Inc.

    Inventor： Mark Bradley Davis ,  David James Borland

    IPC: G06F13/28 ,  G06F13/40

    CPC classification number: G06F13/28 ,  G06F13/4027 ,  G06F15/7892 ,  G06F2213/0038

    Abstract: Embodiments of the technology can provide the flexibility of fine-grained dynamic partitioning of various compute resources among different compute subsystems on an SoC. A plurality of processing cores, cache hierarchies, memory controllers and I/O resources can be dynamically partitioned between a network compute subsystem and a server compute subsystem on the SoC.

    Abstract translation: 该技术的实施例可以提供在SoC上的不同计算子系统之间的各种计算资源的细粒度动态划分的灵活性。 可以在SoC上的网络计算子系统和服务器计算子系统之间动态地划分多个处理核心，高速缓存层次结构，存储器控制器和I / O资源。

    EXTRACTING DEBUG INFORMATION FROM FPGAS IN MULTI-TENANT ENVIRONMENTS
    17.
    发明申请
    EXTRACTING DEBUG INFORMATION FROM FPGAS IN MULTI-TENANT ENVIRONMENTS 审中-公开

    公开(公告)号：US20190293715A1

    公开(公告)日：2019-09-26

    申请号：US16422725

    申请日：2019-05-24

    Applicant: Amazon Technologies, Inc.

    Inventor： Mark Bradley Davis ,  Christopher Joseph Pettey ,  Asif Khan ,  Islam Mohamed Hatem Abdulfattah Mohamed Atta

    IPC: G01R31/317 ,  G01R31/3177 ,  G06F11/36 ,  G01R31/28

    Abstract: Methods and apparatus are disclosed for programming reconfigurable logic devices such as FPGAs in a multi-tenant server environment. In one example, a computing host includes one or more processors configured to execute a supervisor process and two or more user processes and a single FPGA integrated circuit configured into a plurality of partitions. The partitions include a host logic partition that is accessible only to the supervisor process executing on the computing host, and two or more accelerator partitions. Each of the accelerator partitions is configured to include a virtual debug unit with a logic analyzer that collects logic signals generated by logic within the respective accelerator partition and sends debug data indicating values of the logic signals to one of the user processes. In some examples, the host logic partitions and/or the accelerator partitions can be independently reprogrammed of each other within their respective portions of the single FPGA.

    Configurable logic platform
    18.
    发明授权
    Configurable logic platform 有权

    公开(公告)号：US10223317B2

    公开(公告)日：2019-03-05

    申请号：US15279232

    申请日：2016-09-28

    Applicant: Amazon Technologies, Inc.

    Inventor： Islam Atta ,  Christopher Joseph Pettey ,  Asif Khan ,  Robert Michael Johnson ,  Mark Bradley Davis ,  Erez Izenberg ,  Nafea Bshara ,  Kypros Constantinides

    IPC: G06F13/40 ,  G06F9/445 ,  G06F13/42 ,  G06F15/78

    Abstract: The following description is directed to a configurable logic platform. In one example, a configurable logic platform includes host logic and a reconfigurable logic region. The reconfigurable logic region can include logic blocks that are configurable to implement application logic. The host logic can be used for encapsulating the reconfigurable logic region. The host logic can include a host interface for communicating with a processor. The host logic can include a management function accessible via the host interface. The management function can be adapted to cause the reconfigurable logic region to be configured with the application logic in response to an authorized request from the host interface. The host logic can include a data path function accessible via the host interface. The data path function can include a layer for formatting data transfers between the host interface and the application logic.

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