公开(公告)号：US09621156B2

公开(公告)日：2017-04-11

申请号：US14109249

申请日：2013-12-17

Applicant: Analog Devices Global

Inventor： David Aherne

IPC: H03K17/00 ,  H03K17/687

CPC classification number: H03K17/6872 ,  H03K2217/0018

Abstract: An analog switch may be maintained reliably in an off state. The switch comprises: a P-type first transistor having a source, a drain and a gate, a N-type second transistor having a source, a drain and a gate, and a switch control circuit to drive the gates of the first and second transistors. The drain of the first transistor and the source of the second transistor are connected at a first node, and the source of the first transistor and the drain of the second transistor are connected at a second node. When the voltage at the first or second nodes falls outside of a supply voltage range of the switch control circuit, the switch control circuit is operable, in response to a signal to make the switch high impedance, by adjusting the gate voltages of the first transistor and the second transistor.

公开(公告)号：US10725959B2

公开(公告)日：2020-07-28

申请号：US16298373

申请日：2019-03-11

Applicant: Analog Devices Global Unlimited Company

Inventor： David Aherne ,  Jofrey Santillan ,  Wes Vernon Lofamia ,  Paul O'Sullivan ,  Padraig McDaid

IPC: G06F13/42 ,  G06F13/16

Abstract: SPI Round Robin Mode for Single-Cycle MUX Channel Sequencing. SPI round robin mode is an SPI mode applicable for MUX devices control. It allows the MUX output to connect to the next input channel sequentially in just one clock cycle. Configurations can be made such as: clock edge to use (rising/falling), ascending/descending channel sequence, and enabling/disabling the channels to go through. The device supersedes an ADC with built in sequencing and is applicable to multiplexing, switching, instrumentation, process control and isolation application—while retaining SPI device control and operation.

公开(公告)号：US20190293692A1

公开(公告)日：2019-09-26

申请号：US16360356

申请日：2019-03-21

Applicant: Analog Devices Global Unlimited Company

Inventor： David J. Clarke ,  Stephen Denis Heffernan ,  Nijun Wei ,  Alan J. O'Donnell ,  Patrick Martin McGuinness ,  Shaun Bradley ,  Edward John Coyne ,  David Aherne ,  David M. Boland

IPC: G01R19/165 ,  G01R31/00 ,  G01R31/28 ,  H01L23/525 ,  H01L27/02 ,  H01L23/60 ,  H01L23/62 ,  H02H9/04

Abstract: The disclosed technology generally relates to electrical overstress protection devices, and more particularly to electrical overstress monitoring devices for detecting electrical overstress events in semiconductor devices. In one aspect, an electrical overstress monitor and/or protection device includes a two different conductive structures configured to electrically arc in response to an EOS event and a sensing circuit configured to detect a change in a physical property of the two conductive structures caused by the EOS event. The two conductive structures have facing surfaces that have different shapes;

公开(公告)号：US10338132B2

公开(公告)日：2019-07-02

申请号：US15291742

申请日：2016-10-12

Applicant: Analog Devices Global

Inventor： Edward John Coyne ,  Alan J. O'Donnell ,  Colm Patrick Heffernan ,  Kevin B. Manning ,  Mark Forde ,  David J. Clarke ,  Thomas G. O'Dwyer ,  David Aherne ,  Michael A. Looby

IPC: G01R31/28

Abstract: The disclosed technology generally relates to integrated circuit devices with wear out monitoring. An integrated circuit device includes a core circuit and a wear-out monitor device. The wear-out monitor device configured to adjust an indication of wear out of the core circuit regardless of whether the core circuit is activated The integrated circuit further includes a sensing circuit coupled to the wear-out monitor device and configured to detect an electrical property of the wear-out monitor device that is indicative of a wear-out level of the core-circuit.

公开(公告)号：US20190128939A1

公开(公告)日：2019-05-02

申请号：US15801132

申请日：2017-11-01

Applicant: Analog Devices Global

Inventor： Alan J. O'Donnell ,  David Aherne ,  Javier Alejandro Salcedo ,  David J. Clarke ,  John A. Cleary ,  Patrick Martin McGuinness ,  Albert C. O'Grady

IPC: G01R31/00 ,  H02H1/00 ,  G08B21/18

Abstract: Aspects of this disclosure relate to detecting and recording information associated with electrical overstress (EOS) events, such as electrostatic discharge (ESD) events. For example, in one embodiment, an apparatus includes an electrical overstress protection device, a detection circuit configured to detect an occurrence of the EOS event, and a memory configured to store information indicative of the EOS event.

公开(公告)号：US20180159523A1

公开(公告)日：2018-06-07

申请号：US15370564

申请日：2016-12-06

Applicant: Analog Devices Global

Inventor： Jofrey G. Santillan ,  David Aherne

IPC: H03K17/16

CPC classification number: H03K17/165 ,  H03K2217/0054

Abstract: A charge injection compensation circuit compensates for charge injection by a field-effect transistor (FET) switch regardless of a supply voltage. The charge injection compensation circuit includes a main switch that injects charge into an electronic circuit when switched off, and a charge storage device that stores the injected charge until it can be dissipated to a dissipating node. Upon the main switch being controlled to switch off, a pulse generator circuit controls a charge storage switch to switch on to transfer the charge injected from the main switch to the charge storage device and then switch off. A dissipation circuit dissipates the charge from the charge storage device to a dissipating node.

公开(公告)号：US09871373B2

公开(公告)日：2018-01-16

申请号：US14671767

申请日：2015-03-27

Applicant: Analog Devices Global

Inventor： Alan J. O'Donnell ,  David Aherne ,  Javier Alejandro Salcedo ,  David J. Clarke ,  John A. Cleary ,  Patrick Martin McGuinness ,  Albert C. O'Grady

IPC: H02H3/22 ,  H02H9/04 ,  H02H9/02 ,  H01L27/02

CPC classification number: H02H9/04 ,  H01L27/0248 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/181 ,  H02H9/02 ,  H02H9/042 ,  H02H9/046 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Aspects of this disclosure relate to detecting and recording information associated with electrical overstress (EOS) events, such as electrostatic discharge (ESD) events. For example, in one embodiment, an apparatus includes an electrical overstress protection device, a detection circuit configured to detect an occurrence of the EOS event, and a memory configured to store information indicative of the EOS event.

公开(公告)号：US20170299649A1

公开(公告)日：2017-10-19

申请号：US15291742

申请日：2016-10-12

Applicant: Analog Devices Global

Inventor： Edward John Coyne ,  Alan J. O'Donnell ,  Colm Patrick Heffernan ,  Kevin B. Manning ,  Mark Forde ,  David J. Clarke ,  Thomas G. O'Dwyer ,  David Aherne ,  Michael A. Looby

IPC: G01R31/26

CPC classification number: G01R31/2879 ,  G01R31/2874

Abstract: The disclosed technology generally relates to integrated circuit devices with wear out monitoring. An integrated circuit device includes a core circuit and a wear-out monitor device. The wear-out monitor device configured to adjust an indication of wear out of the core circuit regardless of whether the core circuit is activated The integrated circuit further includes a sensing circuit coupled to the wear-out monitor device and configured to detect an electrical property of the wear-out monitor device that is indicative of a wear-out level of the core-circuit.

公开(公告)号：US20160285255A1

公开(公告)日：2016-09-29

申请号：US14671767

申请日：2015-03-27

Applicant: Analog Devices Global

Inventor： Alan J. O'Donnell ,  David Aherne ,  Javier Alejandro Salcedo ,  David J. Clarke ,  John A. Cleary ,  Patrick Martin McGuinness ,  Albert C. O'Grady

IPC: H02H9/04 ,  H02H9/02

CPC classification number: H02H9/04 ,  H01L27/0248 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/181 ,  H02H9/02 ,  H02H9/042 ,  H02H9/046 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Aspects of this disclosure relate to detecting and recording information associated with electrical overstress (EOS) events, such as electrostatic discharge (ESD) events. For example, in one embodiment, an apparatus includes an electrical overstress protection device, a detection circuit configured to detect an occurrence of the EOS event, and a memory configured to store information indicative of the EOS event.

Abstract translation: 本公开的方面涉及检测和记录与电应力（EOS）事件相关的信息，例如静电放电（ESD）事件。 例如，在一个实施例中，一种装置包括电过压保护装置，被配置为检测EOS事件的发生的检测电路，以及被配置为存储指示EOS事件的信息的存储器。