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    Detecting a timeout of elements in an element processing system
    12.
    发明申请
    Detecting a timeout of elements in an element processing system 有权
    检测元素处理系统中元素的超时

    公开(公告)号：US20050268144A1

    公开(公告)日：2005-12-01

    申请号：US11100157

    申请日：2005-04-06

    Applicant: Andreas Doering ,  Silvio Dragone

    Inventor： Andreas Doering ,  Silvio Dragone

    IPC: G06F1/12 ,  G06F1/14

    CPC classification number: G06F1/14

    Abstract: Provides methods, systems and apparatus for timer management of an element processing system wherein timer intervals related to elements to be processed can be handled in a time-efficient manner. An example method is a method for detecting a timeout of elements in an element processing system wherein a timer value, indicating a timeout interval with respect to a given time base, is assigned to each of the elements when processed. From a number of elements processed, the timer value indicating a minimum timeout interval to expire is determined out of the number of timer values assigned to the number of elements being processed.

    Abstract translation: 提供用于元素处理系统的定时器管理的方法，系统和装置，其中可以以时间有效的方式处理与要处理的元件相关的定时器间隔。 示例性方法是用于检测元素处理系统中的元素的超时的方法，其中指示相对于给定时基的超时间隔的定时器值在被处理时被分配给每个元素。 从处理的多个元素中，从分配给正在处理的元素数量的定时器值的数量中确定指示到期的最小超时间隔的定时器值。

    Method and apparatus for using FPGA technology with a microprocessor for reconfigurable, instruction level hardware acceleration
    13.
    发明申请
    Method and apparatus for using FPGA technology with a microprocessor for reconfigurable, instruction level hardware acceleration 有权
    使用FPGA技术与微处理器进行可重配置，指令级硬件加速的方法和装置

    公开(公告)号：US20050097305A1

    公开(公告)日：2005-05-05

    申请号：US10696865

    申请日：2003-10-30

    Applicant: Andreas Doering ,  Silvio Dragone ,  Andreas Herkersdorf ,  Richard Hofmann ,  Charles Kuhlmann

    Inventor： Andreas Doering ,  Silvio Dragone ,  Andreas Herkersdorf ,  Richard Hofmann ,  Charles Kuhlmann

    IPC: G06F9/00 ,  G06F9/318 ,  G06F9/38 ,  G06F15/78

    CPC classification number: G06F9/3877 ,  G06F9/30181 ,  G06F9/3897 ,  G06F15/7867

    Abstract: A method for dynamically programming Field Programmable Gate Arrays (FPGA) in a coprocessor, the coprocessor coupled to a processor, includes: beginning an execution of an application by the processor; receiving an instruction from the processor to the coprocessor to perform a function for the application; determining that the FPGA in the coprocessor is not programmed with logic for the function; fetching a configuration bit stream for the function; and programming the FPGA with the configuration bit stream. In this manner, the FPGA are programmable “on the fly”, i.e., dynamically during the execution of an application. The hardware acceleration and resource sharing advantages provided by the FPGA can be utilized more often by the application. Logic flexibility and space savings on the chip comprising the coprocessor and processor are provided as well.

    Abstract translation: 一种用于在协处理器中动态编程现场可编程门阵列（FPGA）的方法，所述协处理器耦合到处理器，包括：开始处理器执行应用程序; 从所述处理器接收到所述协处理器的指令以执行所述应用的功能; 确定协处理器中的FPGA不是用该功能的逻辑编程的; 获取功能的配置位流; 并使用配置位流对FPGA进行编程。 以这种方式，FPGA可以“即时”编程，即在执行应用期间动态地编程。 应用程序可以更频繁地利用FPGA提供的硬件加速和资源共享优势。 还提供了包括协处理器和处理器的芯片上的逻辑灵活性和空间节省。

    Exhaust gas turbine and method of operating the same
    14.
    发明授权
    Exhaust gas turbine and method of operating the same 有权

    公开(公告)号：US11795853B2

    公开(公告)日：2023-10-24

    申请号：US17525922

    申请日：2021-11-14

    Applicant: Andreas Doering

    Inventor： Andreas Doering

    IPC: F01N3/20 ,  F01D25/24 ,  B01F23/213 ,  B01F25/313 ,  B01F25/421 ,  B01F27/112 ,  B01F27/053

    CPC classification number: F01N3/2066 ,  B01F23/2131 ,  B01F25/3131 ,  B01F25/31333 ,  B01F25/4231 ,  B01F27/0531 ,  B01F27/112 ,  F01D25/24 ,  B01F2215/044 ,  B01F2215/0422 ,  B01F2215/0495 ,  F01N2610/1453 ,  F05D2300/611

    Abstract: An exhaust gas turbine (30) for expanding exhaust gas, comprising a turbine housing (33) having an inflow housing portion (35) for exhaust gas to be expanded and an outflow housing portion (36) for expanded exhaust gas, a turbine rotor (34) received by the turbine housing (33), the turbine rotor (34) being rotatable about an axis of rotation, a metering means (42) for a reducing agent or a precursor substance of a reducing agent, wherein the reducing agent or the precursor substance can be introduced into the expanded exhaust gas via the metering device (42), and with a swirl atomizer (43), rotating together with the turbine rotor (34), for the reducing agent or the precursor substance, the reducing agent or the precursor substance being atomizable in the expanded exhaust gas via the swirl atomizer (43), the swirl atomizer (43) engaging the turbine rotor (34) at a downstream, hub-side portion of the turbine rotor (34). Downstream of the turbine rotor (34) in extension of the axis of rotation of the turbine rotor (34), an impingement body (44) is arranged for the reducing agent or the precursor substance introduced into the exhaust gas and atomized, wherein a distance of the impingement body (44) from the swirl atomizer (43) corresponds to at most 7 times a diameter of the turbine rotor (34).

    Determining a priority value for a thread for execution on a multithreading processor system
    17.
    发明授权
    Determining a priority value for a thread for execution on a multithreading processor system 失效
    确定线程在多线程处理器系统上执行的优先级值

    公开(公告)号：US08397234B2

    公开(公告)日：2013-03-12

    申请号：US12334678

    申请日：2008-12-15

    Applicant: Andreas Doering ,  Maria Gabrani

    Inventor： Andreas Doering ,  Maria Gabrani

    IPC: G06F9/46

    CPC classification number: G06F9/4831

    Abstract: An apparatus for determining a priority value for a thread for execution on a multithreading processor system includes: a base value register for depositing a priority base value; and an evaluation unit for determining the priority value of the thread for execution on the multithreading processor system subject to the priority base value and an application priority value delivered from a thread's application.

    Abstract translation: 一种用于确定用于在多线程处理器系统上执行的线程的优先级值的装置包括：用于存储优先级基础值的基值寄存器; 以及评估单元，用于根据优先级基数确定在多线程处理器系统上执行的线程的优先级值以及从线程的应用传递的应用优先级值。

    DETERMINING A PRIORITY VALUE FOR A THREAD FOR EXECUTION ON A MULTITHREADING PROCESSOR SYSTEM
    18.
    发明申请
    DETERMINING A PRIORITY VALUE FOR A THREAD FOR EXECUTION ON A MULTITHREADING PROCESSOR SYSTEM 失效
    确定用于执行多功能处理器系统的螺纹的优先级值

    公开(公告)号：US20090183158A1

    公开(公告)日：2009-07-16

    申请号：US12334678

    申请日：2008-12-15

    Applicant: Andreas Doering ,  Maria Gabrani

    Inventor： Andreas Doering ,  Maria Gabrani

    IPC: G06F9/46

    CPC classification number: G06F9/4831

    Abstract: An apparatus for determining a priority value for a thread for execution on a multithreading processor system includes: a base value register for depositing a priority base value; and an evaluation unit for determining the priority value of the thread for execution on the multithreading processor system subject to the priority base value and an application priority value delivered from a thread's application.

    Abstract translation: 一种用于确定用于在多线程处理器系统上执行的线程的优先级值的装置包括：用于存储优先级基础值的基值寄存器; 以及评估单元，用于根据优先级基数确定在多线程处理器系统上执行的线程的优先级值以及从线程的应用传递的应用优先级值。

    File operation management device
    19.
    发明申请
    File operation management device 审中-公开
    文件操作管理设备

    公开(公告)号：US20060036898A1

    公开(公告)日：2006-02-16

    申请号：US11182419

    申请日：2005-07-15

    Applicant: Andreas Doering

    Inventor： Andreas Doering

    IPC: G06F11/00 ,  G06F17/30 ,  G06F12/00

    CPC classification number: G06F16/16

    Abstract: The present invention provides file operation management devices, methods and processing systems which allow better utilization of application-processing units. It also provides file system operation functionality which requires less resources of the application-processing unit and provides a performance increase of the application. It provides a file operation management device for performing file system operations, including a storage interface for coupling to a data storage device, a system-internal data interface for connecting with a processing unit to receive user and/or command data from the processing unit and to transmit status and user data to the coupled processing unit, a file system unit for receiving the user and/or command data via the data interface and for performing the file system operation on the data storage device depending on the user and/or command data received via the data interface.

    Abstract translation: 本发明提供了能够更好地利用应用处理单元的文件操作管理装置，方法和处理系统。 它还提供文件系统操作功能，需要较少的应用程序处理单元资源，并提供应用程序的性能提升。 它提供用于执行文件系统操作的文件操作管理装置，包括用于耦合到数据存储装置的存储接口，用于与处理单元连接以从处理单元接收用户和/或命令数据的系统内部数据接口，以及 将状态和用户数据发送到耦合处理单元，文件系统单元，用于经由数据接口接收用户和/或命令数据，并且用于根据用户和/或命令数据在数据存储设备上执行文件系统操作 通过数据接口接收。

    Coupling a general purpose processor to an application specific instruction set processor
    20.
    发明申请
    Coupling a general purpose processor to an application specific instruction set processor 失效
    将通用处理器耦合到特定于应用程序的指令集处理器

    公开(公告)号：US20050172105A1

    公开(公告)日：2005-08-04

    申请号：US11035934

    申请日：2005-01-14

    Applicant: Andreas Doering ,  Silvio Dragone

    Inventor： Andreas Doering ,  Silvio Dragone

    IPC: G06F9/30 ,  G06F9/318 ,  G06F9/38 ,  G06F15/00

    CPC classification number: G06F9/3877 ,  G06F9/30079 ,  G06F9/3017 ,  G06F9/382 ,  G06F9/3879

    Abstract: Provides methods, systems and apparatus for coupling a general purpose processor (GPP) to an application specific instruction set processor (ASIP) in such a manner that the GPP can include execute instructions that do not normally comprise part of its instruction set architecture (ISA). The GPP is coupled to the ASIP via a coprocessor port such that instructions issued by the GPP to the port are conveyed to a novel pre-decoder module of the ASIP. The pre-decoder module translates the GPP instruction into operation codes for ASIP instructions to be executed in the ASIP or to an address in the ASIP instruction memory that identifies a start address for a plurality of ASIP instructions defining a complex application specific function. Once the ASIP has executed the instructions it shares the result of the execution with the GPP. In this way, the GPP takes advantage of the ASIP in its ability to more quickly execute an application specific program/procedure.

    Abstract translation: 提供用于将通用处理器（GPP）耦合到应用特定指令集处理器（ASIP）的方法，系统和装置，使得GPP可以包括通常不包括其指令集架构（ISA）的一部分的执行指令， 。 GPP通过协处理器端口耦合到ASIP，使得GPP向端口发出的指令被传送到ASIP的新型预解码器模块。 预解码器模块将GPP指令转换为在ASIP中执行的ASIP指令的操作码或ASIP指令存储器中的一个地址，该地址标识用于定义复杂的专用功能的多个ASIP指令的起始地址。 一旦ASIP执行了指令，它将与GPP共享执行结果。 以这种方式，GPP利用ASIP更快地执行特定应用程序/程序的能力。

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